10-13-2009 02:28 PM
In the Virtex-6 Select IOuser guide ug361.pdf it explains the DCI cascading for banks in the same column. Does anybody knows if I can use two different cascading in the same column? Example: if Banks A, B, C and D are in sequence in a column, A and B are 1V8 and C and D 2V5, can I connect VRP/VRN resistors only on banks A and C, cascading A to B and C to D? If anyone can answer, thanks,
10-13-2009 02:54 PM
No. The cascading assumes that all IO are operating on the same Vcco potential.
For each Vcco that is different, reference resistors are required in that bank.
The DCI block samples the reference blocks, and then transmits the settings used in that block to match pull-up, and pull-down to all DCI IO pins in that bank, and to other banks (if the Vcco is the same) in the cascade feature.
Xilinx San Jose
10-13-2009 02:59 PM
As I re-read you question, it sounds like you don't mix the Vcco. A=B, and C=D. So then the question is can I succeed to cascade A to B, C to D?
Don't know, but since that doesn't violate the "normal use," then why not? If cascade allows for A-B, and also separately C-D, then it isn't violating anything. Is it possible to set the attributes to do A to B, and C to D?
I will look through the user's guide, but you may have to bring up FPGA_editor, and look at the bits themselves to be sure it is possible,
Xilinx San Jose
10-14-2009 05:46 AM
Your last interpretation of my question is right I think, it is something like this I wanted to do if it's possible:
|A|<- here I connect VRP/VRN referenced to 1V8
|C|<- here I connect VRP/VRN referenced to 2V5
With these conditions:
1- Banks A,B,C and D in the same column.
2- Banks A and B are VCCO_1V8 (connecting DDR2 for example)
3- Banks C and D are VCCO_2V5 (a RGMII interface for example)
So the question: does it work to cascade B from A AND D from C with different VCCOs?
As you said, the user guide doesn't put any constraint to this situation...
11-17-2009 08:15 AM
Simulating this scenario, it worked, just requiring that the "Master" bank (the one with the VRN/VRP resistors) must have at least one pin declared as any one of the DCI standards (LVDCI) to allow the cascading to the other one, even with different VCCOs in the same column.
But we changed the design to avoid this situation, so we aren't going to have an answer so soon...