Virtex® Family FPGAs

[vbmazter]

Hi,

I'm using a Virtex-6 with DSP48E and I am not sure whether I understood their latency.

Some of them get inferred by the synth tools, which is great. Something like `A <= B*C` gets mapped to one of those.

From that, I am thinking that the DSP48E performs this multiplication in one cycle, is this really the case?

On the other hand, if it were any different it would not make sense to me. It's just that I read UG369 "Virtex-6 FPGA DSP48E1 Slice", and in the block diagrams a lot of registers show up, the description isn't really clear to me...

Maybe someone can enlighten me, or just confirm ;)

Thanks!

[austin]

v,

http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf

Table 58

Contains the performance information.

Yes, operations are completed in one clock cycle, but getting them into, and out of the DSP48 may require registers (pipe-lining).  It depends on your clock requirements (get close to the Fmax of the DSP48E and you need pipeline stages, less fast, and you may not).  The built in registers are there to facilitate very fast designs.

Careful floor-planning, and register selection, and placement of the BRAMs (if they are used) is all part of getting the fastest speeds (at the expense of a little latency).

[ywu]

All the registers in the DSP48 block diagram are optional.

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vbmazter wrote:

Hi,

I'm using a Virtex-6 with DSP48E and I am not sure whether I understood their latency.

Some of them get inferred by the synth tools, which is great. Something like `A <= B*C` gets mapped to one of those.

From that, I am thinking that the DSP48E performs this multiplication in one cycle, is this really the case?

On the other hand, if it were any different it would not make sense to me. It's just that I read UG369 "Virtex-6 FPGA DSP48E1 Slice", and in the block diagrams a lot of registers show up, the description isn't really clear to me...

Maybe someone can enlighten me, or just confirm ;)

Thanks!

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