Virtex® Family FPGAs

[80216e]

Dear all,

I'd like to use the high speed transceiver "GTX" modules available on the Virtex to capture high speed data ~ 5Gbps. In order to process these data on the FPGA with internal clock speeds ~ 300MHz, A serial to parallel operation is required. I was wondering if this demuxing functionality is part of the GTX ? and how can I change the demuxing ratio? I searched in the user guide but couldn't find a clear answer to my inquiry.

Thanks in advance.

Best Regards

[roym]

Yes the GTX will outpit the serial input data.  You should consult the GTX user guide or the coregen mdule for the GTX t o get a better feel for what widths are supported.

[80216e]

Thank you ery much for your reply. I'll beg your pardon to dig little bit more on this.

So I learned there is a First-in First-out FIFO buffer that will be filled by the GTX, and the FPGA can then read the data from it in parallel fashion. Now the question is: Is this FIFO buffer shared by all the GTX modules, which may limit the total number of IO's I can run at the same time, or is there an independent FIFO for each GTX/quad?

Really appreciate your help.

Best Regards,

Ayman

[roym · Accepted solution]

Each GT has it's own IO so you can easily input more data than you know what to do with.

[80216e]

Thanks! that was helpful.

Best Regards,

Ayman