Virtex® Family FPGAs

[technovlsi]

I have simulated my vhdl program and the time needed is 80 us. Now when i run this program on board Virtex 5 ,then how will i know about the execution time ? i have assigned the clock frequency at 100 MHz. i think there will be difference in software simulation time and hardware simulation time.. Please help .

[bassman59]

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technovlsi wrote:

I have simulated my vhdl program and the time needed is 80 us. Now when i run this program on board Virtex 5 ,then how will i know about the execution time ? i have assigned the clock frequency at 100 MHz. i think there will be difference in software simulation time and hardware simulation time.. Please help .

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VHDL is NOT A PROGRAMMING LANGUAGE.

You are NOT WRITING A SEQUENTIALLY-EXECUTED COMPUTER PROGRAM.

[mcgett]

You are developing hardware that will run constantly, so the execution time is until the board is powered off.

Hardware timing is usually referred to as latency for a data flow design.  Data will be present at the inputs of the design and it will take some numbers of clock cycles before it is full processed and presented on the outptus of the design.  The total number of clock cycles is the latency.  In most data flow designs, the next output will appear on the outputs the next clock cycle.   Taking the number of clock cycles and multipling it by the clock period will give you the real time between the input and output time.