04-25-2011 02:46 PM
2) I set the IOSTANDARD to LVCMOS33 and I am using an Eval Board, so I would expect the logic level to be 3.3V
3) I haven't tried routing the clock back out to a header to see with my scope. I will do that next.
04-25-2011 02:58 PM
> 2) I set the IOSTANDARD to LVCMOS33 and I am using an Eval Board, so I would expect the logic level to be 3.3V
The IOSTANDARD attribute does not override the physical conditions that the FPGA is set to. What is the actual voltage on the VCCO_EXP rail?
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04-25-2011 02:59 PM
More update, it looks like chipscope does show the clock input after changing to IO...CC, But none of the logic clocked to that input Clk does not work. (i.e. Register/counter/etc)