Virtex® Family FPGAs

[ribalda]

Hello

In my design the fpga is programmed trough a parallel flash... this allways works.  The problem arrives when I want to launch a reprog through the hwicap interface.This is working around 95% of the times, but the other 5%, the fpga does not start :(.

I have read back the fpga registers with impact on an error condition and this is what i get:

1: VCCAUX Supply: Current Reading:   2.499 V, Min. Reading:   2.496 V, Max. Reading:   2.499 V
'1': Reading status register contents...
CRC error                                                                  :         0
Decryptor security set                                                     :         0
DCM locked                                                                 :         1
DCI matched                                                                :         1
End of startup signal from Startup block                                   :         1
status of GTS_CFG_B                                                        :         0
status of GWE                                                              :         1
status of GHIGH                                                            :         1
value of MODE pin M0                                                       :         0
value of MODE pin M1                                                       :         1
Value of MODE pin M2                                                       :         0
Internal signal indicates when housecleaning is completed                  :         1
Value driver in from INIT pad                                              :         1
Internal signal indicates that chip is configured                          :         1
Value of DONE pin                                                          :         1
Indicates when ID value written does not match chip ID                     :         0
Decryptor error Signal                                                     :         0
System Monitor Over-Temperature Alarm                                      :         0
startup_state[18] CFG startup state machine                                :         0
startup_state[19] CFG startup state machine                                :         0
startup_state[20] CFG startup state machine                                :         1
E-fuse program voltage available                                           :         0
SPI Flash Type[22] Select                                                  :         1
SPI Flash Type[23] Select                                                  :         1
SPI Flash Type[24] Select                                                  :         1
CFG bus width auto detection result                                        :         1
CFG bus width auto detection result                                        :         1
Reserved                                                                   :         0
BPI address wrap around error                                              :         0
IPROG pulsed                                                               :         0
read back crc error                                                        :         0
Indicates that efuse logic is busy   

Which is exactly he same as when the fpga boots except of the GTS_CFG_B=0.

I am kind of stuck with this error, because it is very difficult to replicate, and does not make much sense, specially when you realize that the crc_error is 0 and the GHIGH is 1....

I also have the impression that the error tends to happen when the fpga is "cold"...

Any ideas?

 Thanks!

[rcingham]

"I also have the impression that the error tends to happen when the fpga is "cold""

Stick it in an environmental chamber and make sure. Some signal integrity get worse at low temperatures due to increase in edge slew rates.

[ribalda]

Hello, thanks for your response

If by environmental chamber you meen a freezer :P, we have done some tests, and we don't have a definitive answer, it seems worse, but with an error rate of 5% is difficult to get conclussions.

Thanks

[austin]

r,

Simulate the configuration signals to find the signal integrity problem.  Or, look at the signals with an oscilloscope:  no ringing, no overshoot, no undershoot, clean rise times and fall times.

Any bad signal integrity, look at what you need to do to fix it.

The most common problem is the CCLK.  Check it first.  Read how to distribte the CCLK singal, especially if it goes to more than one device.

Sometimes a series resistor, or a parallel termination (split termination) in the right place solves this problem.

What I can't see is why this happens with HWICAP, and not with the inital load.

Also check the startup sequence.  If you specify that PLLs, DCMs, and DCI must be locked before DONE, sometimes you may get into a "never get there" situation.  Waiting for lock doesn't happen because something else is preventing it.

[austin]

And,

Remember that there is only one configuration interface: if you use JTAG, it will have precedence over the HWICAP, so you may inadvertently lock out the ICAP, and the system will hang, waiting for the ICAP to become free.

[ribalda]

Hello Austin

Thanks for your feedback.

The jtag is not connected, I just connect it when there is a "crash" and I want to read back the status registers.

The CCLK is not connected to anything, since the NOR flash does not need it.

Also, I dont think it is a problem with the reading of the bitstream, otherwise the CRC error will be 1.

I have the impression that there is "something" that does not allow the fpga to enable the IO pins, but I havent found any clue on the doc.

Any ideas?

[rcingham]

"CCLK is not connected to anything"

Floating when JTAG cable not connected? Or pull-up or pull-down?

[ribalda]

The CCLK pin of the FPGA is Not Connected to anything.

I have attached the schematic and the pcb.

Regards