07-14-2011 12:28 AM
I have an ML605 Evaluation Board with the XM104 FMC card and am trying to build an SATA interface. I used the GTX Transceiver Wizard 1.9 to instantiate the core. I chose 150MHz as clock speed (to my understanding this is required for SATA 3 Gbps) and REFCLK0_Q1 as clock source for the RX. For the TX the option "use rx pll" was chosen. The placement is chosen to be in the GTXE1_X0Y4.
In the example design UCF-file it says that the clock pins should be connected to the pins AD5, AD6. From these pins the clock goes into the the IBUFDS_GTXE1 and then to the MGTREFCLK_IN of the SATA core. My problem is now that the PLL of the SATA core won´t lock. So I checked if there is a signal from the REFCLK0_Q1 (named MGTREFCLK0P and MGTREFCLK0N in the GTX Transceiver Guide, UG366) and there doesn´t seem to be an clock signal from these pins. I tried the other clock of the quad, which is connected to the pins AB6 and AB5 and it´s the same here. Do I have to route a clock signal here or did I forget something else?
After some time I thougt about where the 150MHz clock should actually come from and that maybe I have to generate it first (?). To my understanding, there would be two options for generating a 150MHz signal. The first would be to take the system clock (200 MHz) and then use a MMCM module with multiply by 3 and divide by 4 to generate the 150MHz. But I´m not sure this is an adequate solution to clock the GTX transceivers because it might introduce jitter. The second option is to use the Si570 oscillator and following clock divider on the XM104 board. But these devices have to be initialized via the I2C bus first, so I´d have to include a I2C master in my FPGA and somehow I thougt that´s a lot of work just to get a clock signal, so I thought that I maybe just overlooked something.
Any suggestions where to look or what to do or try are greatly appreciated.
Thank you very much, Sandro
07-21-2011 05:17 PM
Yes, you need to initlialize and program the clock oscillators on the XM104 via IIC to get a 150 MHz clock. There is a 156.25 MHz default clock available from the Si570 (GBTCLK1_M2C at pins AK5 and AK6) . You can get the PLL to lock with this and even send-receive OOB signals with this (I've tried it), but to get a device signature from the disk or to send and receive frames for SATA, you need a 150 MHz clock source. The other option : generating a 150MHz clock from the 200MHz system clock source works fine.
09-01-2011 12:44 AM
I'm also trying using the 200Mhz (which is on the ML605) to generate the 150Mhz for 3G line rate SATA-II, but i meet the link unstale issue, the GTX link will work for a while then will go down. And further, the signaurture identity (256 Bytes) can't be correctly receive by my transport layer application.
09-01-2011 07:49 AM
You should not be using the 200 MHz clock that comes in on the SelectIO as the reference clock source for the MGTs.
I am assuming that you are using the FMC-XM104 board with SATA connectors for the the physical interface. This board includes Silicon Labs SI570 (GBTCLK1) and SI5368 (GBTCLK0) programmable clocks that can be set to 150 MHz (or 300 MHz) and used as the MGT reference clock source.
The SATA connectors on the FMC-XM104 are connect to the DP2 and DP3 MGT lanes and on the ML605 the GBTCLK0 is the reference clock for MGT Quad112 that is connected to the DP2 and DP3.
Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
02-28-2013 08:03 AM - edited 02-28-2013 08:04 AM
I am trying to generate a 150 MHz clock for a SATA2 core, I can specify 150 MHz frequency from one of the clock generator outputs and connect it to the sata core via ports section in xps.
I did not understand why I would need to use the MMCM module?
(im using ise 14.4 with ml605 abd xm104 fmc) the interface is not working and i suspect that I am not supplying the clock currectly. the link up led is off