Virtex® Family FPGAs

[sdbzlh]

I got some problems when working on pcie_blk_plus of Virtex5 .

(1)As described in Figure 4-8 in pcie_blk_plus_ug341, signals are changed by the hard core at the rising edge of the trn_clk.I want to know

 whether I can read these signals at the rising edge,or I should wait until the falling edge to read.

(2)I think I should read the signals at the falling edge to avoid  logic hazard .But then another problem comes out :
     If I read signal A at the falling edge ,I want to change the value of  signal B (like trn_rdst_rdy_n ) according to the value of A.

     But the Figure 4-8 indicates that I should change the value of B at the rising edge.
     And I want to complement this function as a basic 3-process state machine drived by trn_clk, the input and output are in operated in a same process controling  combinational logic,so read and write must at the same edge of the trn_clk.
     What should I do?

(3)If I can read the signals at the rising edge then there will be no such problem,I want to know whether this is safe.I think this can be safe

only if trn_clk is given out after some delay to ensure that the signals are safe to read  at the rising edge.

I want to make sure if the PCIE Hard Core has such function.

Thank you for helping me !

[sdbzlh]

Nobody help me for what reason?

 If there is anything I discribed not clearly enough ,please tell me ,I am willing to amend my words.

If my problem is too easy, just give me the solution, I  really appreciate your help.

[seanlj · Accepted solution]

all the data is readed at the rising of trn_clk.