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How CH7301C pins connected to FPGA in ML 506
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05-03-2012 11:23 AM
Hi all,
please I want to know how the Chrontel pins (DE ,H, V, XCLK_N, XCLK_P , ISET , RESET and data(0:11)) connected to the virtex_5 FPGA in ML506 board. From UG347 ,I know that :
SPD pin is connected to T29
SPC pin is connected to U27
GPIO1 pin is connected to N30
Is there another pins must be connected to FPGA to make the CH7301C work in RGB bypass mode?
Re: How CH7301C pins connected to FPGA in ML 506
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05-03-2012 01:55 PM - edited 05-03-2012 02:29 PM
Isn't this information in the ML506 board schematics?
Or are you seeking additional information which is not in the schematics?
In case you do not trust web-based search engines, the ML506 schematics can be found here.
It looks like the FPGA connections to the CH7301C are located on pages 4 and 15 -- but I did not check carefully.
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
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