Virtex® Family FPGAs

[liucheng]

I am trying to use RAM18E1 to construct my own RAM block, and I have checked the RAMB18E1 instantation example in UG363 document. The example works all right, but I do want to initiate the RAM block using INIT_FILE instead of INIT_XX directly in the source code. However, I am not sure the format of the file. I  have tried a few formats, but I have got no lucky yet.

Anyone can help with this? 

I guess the actual format may be realted with the configuration, so I have the instantation code attached.

...

RAMB18E1 #(
// Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
.SIM_COLLISION_CHECK("ALL"),
// DOA_REG, DOB_REG: Optional output register (0 or 1)
.DOA_REG(0),
.DOB_REG(0),
// INITP_00 to INITP_07: Initial contents of parity memory array
//.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
//INIT_00 to INIT_3F: Initial contents of data memory array
//.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
//.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// INIT_A, INIT_B: Initial values on output ports
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("file.mem"), // RAM init file
//.INIT_FILE("NONE"),
.RAM_MODE("TDP"), // "SDP" or "TDP"
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), // "PERFORMANCE" or
// "DELAYED_WRITE"
// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
.READ_WIDTH_A(18), // 0,1,2,4,9,18,36
.READ_WIDTH_B(18), // 0,1,2,4,9,18
.WRITE_WIDTH_A(18), // 0,1,2,4,9,18
.WRITE_WIDTH_B(18), // 0,1,2,4,9,18,36
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
// SRVAL_A, SRVAL_B: Set/reset value for output
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
RAMB18E1_inst (
// Port A Data: 16-bit (each) output: Port A data
.DOADO(data_outA), // 16-bit output: A port data/LSB data output
.DOPADOP(DOPADOP), // 2-bit output: A port parity/LSB parity output
// Port B Data: 16-bit (each) output: Port B data
.DOBDO(data_outB), // 16-bit output: B port data/MSB data output
.DOPBDOP(DOPBDOP), // 2-bit output: B port parity/MSB parity output
// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port
// when RAM_MODE="SDP")
.ADDRARDADDR(addrA), // 14-bit input: A port address/Read address input
.CLKARDCLK(clk), // 1-bit input: A port clock/Read clock input
.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable input
.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable input
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset input
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset input
.WEA(WEA), // 2-bit input: A port write enable input
// Port A Data: 16-bit (each) input: Port A data
.DIADI(data_inA), // 16-bit input: A port data/LSB data input
.DIPADIP(DIPADIP), // 2-bit input: A port parity/LSB parity input

// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port
// when RAM_MODE="SDP")
.ADDRBWRADDR(addrB), // 14-bit input: B port address/Write address input
.CLKBWRCLK(clk), // 1-bit input: B port clock/Write clock input
.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable input
.REGCEB(REGCEB), // 1-bit input: B port register enable input
.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset input
.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset input
.WEBWE(WEBWE), // 4-bit input: B port write enable/Write enable input

// Port B Data: 16-bit (each) input: Port B data
.DIBDI(data_inB), // 16-bit input: B port data/MSB data input
.DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity input
);

[eteam00 · Accepted solution]

Have you read this bit from the mini-FAQ in the New Users Forum README thread?

Block RAM initialisation  link#1  link#2  link#3  link#4  link#5

-- Bob Elkind

[liucheng]

Thanks for your reply and the links. I have seen most of them except the mem-edit part.

Anyway, it is helpful in terms of initializing the memory block. However, I want to have each instance of a single memory block to be initialized with different value and I can replace the initial value without repeating ISE design flow after the first implementation.

I know data2mem command can help solve the problem, but I have hundreds of memory instance to be initialized and I want to put the process in to scripts to handle the initialization automatically. As far I know, there are basically two methods for this purpose.

The first process goes like this.

Find out the mapping between instance name and its physical position.

Keep the mapping into bmm file

Prepare the initial value in files.

data2mem –bm top.bmm –bd file.mem –bt original.bit –o current.bit

This method should be OK according to the data2mem_standalone document. But I have no idea on how to put the process into scripts.

The second process mainly depends on the data2mem document (UG658) on page 28. It seems that the bmm file can be generated automatically when we build the data memory using primitive memory blocks such as RAMB18E1. However, the planAhead 13.3 complains “[NgdBuild 989] Failed to process BMM information (full)” no matter what kind of data format file I have put in INIT_FILE option.

I am not sure if I have misunderstood the tools or something else, and I am really looking forward to your suggestions on the problem.

[liucheng]

I found it on the document, and it should be .mem file.

Thanks for your reply.