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Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009
0

Re: How to generate 12Mhz clk on Virtex5 FPGA.

[ Edited ]

Do you want to say that I need to put series resistors to D[7:0] (Data lines between circuit and FPGA), while writing commands and it should not be there while reading data!!

 

No.  Ringing on data lines is not fatal.  Ringing on write strobe might be fatal.

 

-- Bob Elkind

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