Virtex® Family FPGAs

[seals98]

Dear Experts

I use Virtex 6 which can use IODelay only 31tap.

if i want to exceed more than 31tap, How do I make IO Delay logic ?

I hear that it's possible to make 2 Delay logic for one signal.

First  Delay logic can delay  1 clk period.(2 clk period, 3clk period) 

Second  Delay logic can delay  time wihin 31taps

What kind of macro logic should i use to make more delays else IODELAYE1 ?

[mcgett]

It is not possible to have a larger value than 31 with the IODELAY and it is not possible to cascade two IODELAYs together.

What are you trying to do that you think you need to do this?

[kren]

Do you want to delay clock or data signals?

[bennetfischer]

I also would be curious to know how to add more delay to a signal than it is possible by an IODELAY.

The application where something like that could be useful: The FPGA generates a high speed clock (but slower than the maximum IODELAY value). An external chip receives the clock and returns data with an unknown but constant phase relationship to the clock. By the use of a training pattern from that chip and a sufficiently large variable delay a simple state machine could find the phase relationship and re-position the data appropriately.

But if the delay does not span over a clock period, you cannot measure the phase relationship in every case. A larger IODELAY would solve this issue. But maybe there is a smarter solution to that problem?

[ssvoysky]

I have a similar question.

In xapp872 it is shown how to cascade IODELAY elements. Above you are saying this can not be done. So which is correct? For example I have a source sync interface with a 16 ns period. I want to delay the clock 8 ns for midbit sampling. Is there a good way of doing it in Virtex-5?

Another question.

What is a good way to invert a clock comming in from a pin before it is divided by a BUFR?

Thanks!