Sign In

Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Regular Visitor
anandy
Posts: 35
Registered: ‎05-09-2010
0

How to store P-D plot for radix 4 SRT divider in a Virtex 2 pro board

I am trying to code a radix 4 SRT divider and I am stuck with the quotient selection logic. It seems that the quotient is slected based on a p-d lookup table. Intel had used a PLA to store the p-d entries many years ago. I found that the number of entries are about 1000 and I was wondering whether its possible to store this table in some fast memory like a ROM or RAM so that it can be read within 1 cycle - its important to be readable in 1 cycle as the division will be too slow otherwise.

Moderator
binx
Posts: 117
Registered: ‎09-07-2009
0

Re: How to store P-D plot for radix 4 SRT divider in a Virtex 2 pro board

You can use the RAM in FPGA to build a look up table.