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How to store P-D plot for radix 4 SRT divider in a Virtex 2 pro board
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05-21-2010 08:43 AM
I am trying to code a radix 4 SRT divider and I am stuck with the quotient selection logic. It seems that the quotient is slected based on a p-d lookup table. Intel had used a PLA to store the p-d entries many years ago. I found that the number of entries are about 1000 and I was wondering whether its possible to store this table in some fast memory like a ROM or RAM so that it can be read within 1 cycle - its important to be readable in 1 cycle as the division will be too slow otherwise.
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Re: How to store P-D plot for radix 4 SRT divider in a Virtex 2 pro board
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05-26-2010 01:31 AM
You can use the RAM in FPGA to build a look up table.











