05-26-2011 11:48 PM
your saying you manage to get 16 bits of data from one 8 bit ADC ?
or do you mean two 8 bit streams ?
so you have how many 8 bit streams at what clock frequency ?
05-27-2011 11:01 AM
Sorry, I hope I can make it clear:
I have a ADC, actually there are two 8bit ADCs inside, so there are two samples at 1.5GHz at the output. The ADC has a kind of buffer for thes two samples. There are four 8bit output ports at the ADC, so the benefit is I can capture 4 samples (32 bit) at 750 MHz. But I capture it with a 375 MHz clock at rising and falling clock edge (DDR) to the FPGA, inside the FPGA I do actually the same as in the ADC, buffering and capturing at half the clock rate..
At the end I have these 8x16bits in parallel at 375/2 MHz, that are 16 samples. I have two adjacent samples (16bit) at each of the 8 lines to bring them into fifo's.
For demodulation I will have to adapt these to 16 streams each 8bit (one sample) at the same clock as before, 375/2 MHz.
The question is, if I can handle them, I need to multiply the incoming signal with sin and cos in parallel (split signal) and then filter both I and Q channels!
Hope this makes it clear. Thank you.
05-27-2011 11:18 AM
so you have lets say
adc at M samples per second , 8 bits wide.
inside the FPGA this is split into N parallel streams each 8 bits wide, at a clock speed of 188 MHz ( ish )
so to demodulate that to I/Q
brute force, you need N DDC cores running at 188 MHz.
you need to phase shift the start phase to each core by the ( C* phase step / N) , where C is 0 to N-1
and the phase step needs to be N times the mulitplying frequency..
The v6 should run at 375 Mhz, so you could time multiplex the cores, and only need N/2 instances of the DDC core.
Depending upon the size of the sin / cos used, the size of the I/Q could be 12 or more bits.
thats a lot of data coming out the core.
the normal answwer is to decimate, CIC filter et all.
so to answer your question, yes the core you want will easily fit in a virtex 6,
unless you have lots of other stuff,
05-27-2011 12:41 PM - edited 05-27-2011 01:33 PM
So far there is not much implemented on the V6.
After IQ-Demodulation there will be some processing to reduce the data. Thanks also for the advice for the CIC, I will have a look on it!
So the DDC core itself is not that big? In my case N will be 16 and I need I and Q channel that makes 32 at the end!
Further remarks/suggestions are welcome..now I will give it a try.