05-26-2011 09:10 AM
I have a custom board with Virtex 6 LX240T (1156) and a High Speed ADC (3 GSPS, 8 bit) on it. Now I want to evaluate if I can do IQ-Demodulation inside the FPGA of one ADC channel. The data is coming in at 750 MHz (4 Byte at one tick).
Is there any tool or guide how I can validate if it is possible to implement it on this specific Virtex 6?
I appreciate any hint!
05-26-2011 10:05 AM
so basicaly you need to do a design from scratch,
a long road
get the adc working first,
prove the adc works as expected
design a IQ demodulator
see the logi cores for help
Easy Ah !
05-26-2011 10:38 AM
actually it seems to be easy every time I read a Xilinx Tutorial etc. but mostly it is not..
The ADC works, so I get the data as I want it! But I am not sure if I can handle the demodulation (which basically is similar to DDC) at this high data rate (3 GB/s). If not I have to do the demodulation in analog domain and capture twoi channels at a lower sampling rate.
So, how could I estimate if my digital demodulation approach will work?
05-26-2011 10:49 AM
so you have captured the data into the FPGA,
so you now have data in the fpga, on a single clock ?
what width is the data and what clock is the data in the FPGA
you imply that you have a digital demodulator aproach already worked out,
is that correct ?
05-26-2011 11:59 AM
The data is captured at 375 MHz: 4 parallel ADC-ports á 8 bit diff. signal => 64 bit
Then the data is stored into four registers (each 32 bit) @ 375/2 MHz to work with.
I have to say the ADC-IF is not implemented by myself, it seems that it just uses half rate @ 1.5GSPS instead of 3GSPS!?
I have no specific implementation for the demodulator right now, but as I read it is similar to DDC. The signal has to be multiplied by sin and cos wave and the outcoming I & Q channels have to be filtered (basically)
Thanks for your time!
05-26-2011 12:30 PM
05-26-2011 02:27 PM - edited 05-26-2011 03:00 PM
Sorry, now I am clear about it: the data is 64 bit (8 samples using falling and rising clock edge) @ 375 MHz, then in the next cycle I have 128 bit. These 128 bit are splitted up into 8 parallel streams á 16 bit (two adjacent samples) @ 375/2 MHz!
The ADC gives 4 samples at a clock of 750 MHz, this makes 32 bit @ 750 MHz or 64 bit using DDR @ 375 MHz.with the FPGA. Then there is a kind of DeMUX to make it 128 bit (16 samples) @ 375/2 MHz and splitting it up to 8 x 16 bit!