Virtex® Family FPGAs

[rahulrs84]

Thank you for looking at my post.

Let me describe my project:

I am using an ML605 board with 32 MB BPI flash consisting of two 16 MB partitions: Rev0 is a Golden bitstream (a boot controller) and Rev1 is an experiment bitstream. The board boots up, takes in an experimental bitstream over Ethernet and writes it to slot 2, then uses the ICAP to switch to Slot 2 (multiboot).  The bootcontroller system is a Microblaze-AXI basesystem.

This set up works when I do things in standalone mode. The experimental bitstream loads up. When I warm reset the board using JPROGRAM over iMPACT, it works and the boot controller comes back up.

When I move the same system to a Linux system (little endian cross-compilation for MB-AXI), the IPROG command gets stuck and hangs up the kernel and does NOT switch to slot 2. The warm RESET also does NOT work.

I have tried the following three methods:

* Modifying the reset.c in Linux tree to do the ICAP switching

* Userspace driver to set up ICAP registers.

* Kernel driver to do the ICAP multiboot

All of these result in the Linux kernel hanging up.

My IPROG sequence looks like this:

iprog_sequence[iter++] = 0xFFFFFFFF ;
iprog_sequence[iter++] = 0xAA995566;
iprog_sequence[iter++] = 0x20000000;
iprog_sequence[iter++] = 0x30020001;
// WBSTAR Address
iprog_sequence[iter++] = (u32)((u32)(1 << 28) + (u32)(1 << 27) + (u32)(1 << 26) + (u32)0x01000000);
iprog_sequence[iter++] = 0x30008001;
iprog_sequence[iter++] = 0x0000000F;
iprog_sequence[iter++] = 0x20000000;

Am I missing something in this ? 

Does IPROG in a Linux environment require something that is different from Standalone ?

I would appreciate any insight or ideas in this regard.

Thanks again for looking.

Rahul

[mcgovern]

Hi,

Your command sequence looks correct.

There are some things you should check -

Can you Readback the IDCODE with ICAP? Try this to verify your CS and RDWR timing is correct.

On the board - how are RS pins set? These will what address you load from.

How do you set your Multiboot address? Is this set correctly in the bit file?

When the system fails check the Status Register usign iMPACT - Debug -> Read Device Status - This will tell you some things about the failure in the BOOTSTS register

-P

[rahulrs84]

Sorry for the delay in replying back. I was busy with some other projects.

I was able to read BOOTSTS and Status registers using ICAP and I noticed that sending the same frame under Linux and in standalone, the Linux system was going into Fallback mode (FALLBACK bit was high)

Also I noticed that I couldnt access the Microblaze on the Fallback bitstream using XMD -> "connect mb mdm".

Is it a better idea to pass the IPROG using custom hardware and FIFO instead of passing it using software and drivers ?

Any clues ? 

Thanks

RRS

********** ADDED *************

I saw an error "BPI Address Counter Wrap Error" bit to be high in ImPACT, I wonder what are the potential causes ??