Virtex® Family FPGAs

[andreyl]

Hello All,

I do use ISERDES_NODELY for camera link application. I do have 4 Camera link input blocks, each one has four signal differential pairs inputs and additional input clock differential pair(for each block). Differential clocks drive IBUFGDS, while IBUFGDS single ended output drives BUFIO and BUFR(as suggested in XAPP855) and now the point: I getting a placement error like this:

"Place:728 - I/O component "DVID_CH_3_RXCLK_P" drives BUFIO component
   "U1/U1/BUFIO_CH_3" and BUFR component "U1/U1/BUFR_CH_3". The I/O component
   must be placed into a clock capable I/O site in the same region as its
   load(s). Please  make sure such placement is possible.

and like this:

Place:688 - I/O "DVID_CH_3_RXCLK_P" drives the I/O clock buffer (BUFIO)
   "U1/U1/BUFIO_CH_3". This I/O must be placed on a clock capable I/O site and
   the BUFIO component must be placed on the corresponding BUFIO site. The
   following issue has been detected:
   Some of the logic associated with this structure is locked. This should cause
   the rest of the logic to be locked.  A problem was found where we should
   place BUFIO U1/U1/BUFIO_CH_3 off the edge of the chip in order to satisfy the
   relative placement requirement of this logic.

The errors are related to all my input differential clocks(I posted just an example). I found out that such clocks must be connected to "clock capable" I/Os,  in fact they are not connected there, but they are connected to "Global clock" ports. The board is already exixst and just waiting for firmware. I do use Virtex5 XC5VLX50 ff676.

Could somebody help me to figure it out?

Thanks,

Andrey

[andreyl]

Can I use a BUFG or BUFC instead of BUFIO?

[barryabrown]

The following is from the V5 User's Guide, ug190.  It indicates you can use a DCM or PLL, and you can drive either of these from the global clock input.

Barry

ISERDES_NODELAY Clocking Methods

Networking Interface Type

The phase relationship of CLK and CLKDIV is important in the serial-to-parallel

conversion process. CLK and CLKDIV are (ideally) phase-aligned within a tolerance.

There are several clocking arrangements within the FPGA to help the design meet the

phase relationship requirements of CLK and CLKDIV. The only valid clocking

arrangements for the ISERDES_NODELAY block using the networking interface type are:

• CLK driven by BUFIO, CLKDIV driven by BUFR

• CLK driven by DCM, CLKDIV driven by the CLKDV output of the same DCM

• CLK driven by PLL, CLKDIV driven by CLKOUT[0:5] of same PLL

[andreyl]

Hello Barry,

Thanks for replay. I do not want to use DCM and I sow the options from ug190. The question is what would happen if BUFIO will be changed to BUFG(or BUFCF). BUFIO is definitely faster, but I can not use it. If BUFG and BUFCF are acceptable options, which one is better?

Thanks,

Andrey

[roym]

The options listed in Barry's post are the only ones supported.  There are other topologies that might work, but I'm afraid you'd be on your own to test and qualify them. 

To answer your specific question BUFG would be the one to choose if you can't use the PLL option.

-R

[andreyl]

Hi Roy,

Thanks. I have changed BUFIO to BUFG, so now placement has been passed. Hopefully it will work.

Andrey

[roym]

You're welcome andreyl, 

I feel compelled to be clear about this, though, hopefully is not a good way to go if your designing for a commercial product.  I still recommend a PLL so you can say its guaranteed to work and get factory support if it doesn't.

-R

[andreyl]

Hi Roy,

Meanwhile I'm facing another problem, but with same relation. Please see error massage below. Using PLL/DCM can help to solve it? ..or there is another solution, to use constrains, but how?

Place:909 - Regional Clock Net "U1/U2/CLK48_TX_CH" cannot possibly be routed to component
   "U1/U2/OSERDES_DVID_CH_D20" (placed in clock region "CLOCKREGIONP_X1Y2"), since it is too far away from source BUFR
   "U1/U2/BUFR_TX_CH" (placed in clock region "CLOCKREGION_X0Y3"). The situation may be caused by user constraints, or
   the complexity of the design. Constraining the components related to the regional clock properly may guide the tool
   to find a solution.
   To debug your design with partially routed results, please allow map/placer to finish the execution (by setting
   environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).

Thanks,

Andrey

[roym]

I'm guessing the BUFR is not in the same region as the IO's.  A PLL would fix this.

-R