Virtex® Family FPGAs

[bujosa]

I need to instantiate a whole bunch of IO buffers (OBUFDS for example) that are mosly buses.  Do I really have to do this for each bit?  Is there a way to instantiate IO buffers for buses in a compact form rather than breaking it out into each bit?

I am using Virtex-6 and verilog.  Is something like this valid?

OBUFDS #(

.IOSTANDARD("DIFF_SSTL18_II_DCI"))

inst_bus_name(

.O(out_bus_p[31:0]),

.OB(out_bus_n[31:0]),

.I(to_pad_bus[31:0])

);

[gszakacs · Accepted solution]

For a bus you should use an array of instances like:

OBUFDS #(

.IOSTANDARD("DIFF_SSTL18_II_DCI"))

inst_bus_name [31:0](

.O(out_bus_p[31:0]),

.OB(out_bus_n[31:0]),

.I(to_pad_bus[31:0])

);

For instance arrays the rules are:

Port connections must be either A exactly the size of the module port or B exactly the size

of the module port times the number of instances in the array.

For case A all instances get the same connection (useful for clock and reset for example).

For case B each instance gets a bit slice of the vector where the bit slice width is the module

port size.

HTH,

Gabor

[krishna11283]

You should use below code to infer 32 OBUFs 

 genvar i;
   generate
      for (i=0; i < 32; i=i+1)
      begin: inst_32         

       OBUFDS #(

       .IOSTANDARD("DIFF_SSTL18_II_DCI"))

       inst_bus_name(

       .O(out_bus_p[i]),

       .OB(out_bus_n[i]),

       .I(to_pad_bus[i])

        );

       end
   endgenerate

Hope this helps..

[bujosa]

This would result in 32 OBUFDS, but would they all have the same instance name "inst_bus_name"?  Is that legal?  seems like the instance name needs to increment also like in the first suggested solution.

[gszakacs]

In both the array of vectors and the generate loop, the instance name will include the

numeric subscript.  I usually find arrays of instances to be easier to use and easier

to read in the source code.  They were created for just this sort of problem and have

been in the Verilog standards since 1995.  Generate loops were added for Verilog 2001

and allow more complex structures, but in my opinion become a bit harder to read.

If you needed to have interconnects that don't follow the pattern of the instance array,

however you need to use a generate loop.  For example you could modify the generate

loop to invert the bit order as it goes through the buffers by just changing the index on

the buffer outputs to [31-i] instead of [i].

-- Gabor