Virtex® Family FPGAs

[benbenqiao]

Hi,

I'm working on a virtex 4-XC4VSX35_FF668 board. And we want to tranfer some data from the FPGA to PC, while there is only the jtag port available to us. Is there any way to do this? For example , configure the jtag to an uart so we could use that uart to transfer data? I google the problem, and couldn't find any tutorial on this.  Thanks a lot!

Thanks

Ben

[gszakacs · Accepted solution]

Probably the easiest (although not too easy) solution is to use the EDK to make an

embedded processor with the debugger port enabled as the standard in/out.  Then

the embedded CPU can talk to a debug window on the PC using standard I/O.

If you don't have the Embedded edition or EDK, look for BSCAN_VIRTEX4 in the documentation.

This allows your user logic to directly access JTAG signals once the design is running, however

it would take some work at both the FPGA and PC ends to make this work like a serial port.

-- Gabor

[benbenqiao]

Thanks a lot!

[benbenqiao]

Hi Gabor,

I find the doc for BSCAN_VIRTEX4. But I'm still not clear how to use it. I od appreciate if you could give me any example. Thanks a lot. Our project is kind of urgent.

Thanks

Ben

[gszakacs]

I don't have an example becuase the last time I used any sort of BSCAN primitive it was for

Spartan XL, which was roughly the equivalent of the XC400XL series.  However to use the

primitive you need to read three documents:

1) The V6 configuration user guide, which describes the pins of the primitive.

2) The V6 Libraries guide for HDL designs, which describes how to instantiate the primitive.

3) The Synthesis and simulation guide, which describes how to build a test bench for

the JTAG (BSCAN) primitives.

The latter two documents are available from the Project Navigator via:  Help --> Software manuals

If you just wanted to use the TDI and TDO pins as Rx and Tx data like a UART, it looks like

you can do it with a minimum of effort.  The TDI pin comes out of the BSCAN primitive,

and there is a TDO input to the primitive for driving the TDO pin.  However the desciption

says that TDO is latched on a falling edge of TCK, so you would need to have some

way of clocking TCK for this to work.  What's not clear to me is if the TDO will always be

driven by the user logic in this case, or if you need to issue a USER JTAG instruction to

make that happen.  In the first case, you could just tie TMS high when using the pins

as a UART - keeping the JTAG logic reset and preventing undesired side-effects.

-- Gabor

[benbenqiao]

Hi Gabor,

Thank you so much! I will read these doc and try to figure it out.  And could you show me your BSCAN  example for Spartan XL? I think it will be a great help for our project. Thanks a lot!

Thanks

Ben

[gszakacs]

---

benbenqiao wrote:

Hi Gabor,

Thank you so much! I will read these doc and try to figure it out.  And could you show me your BSCAN  example for Spartan XL? I think it will be a great help for our project. Thanks a lot!

Thanks

Ben

---

Unfortunately, the BSCAN from the older parts is a completely diferent animal.  I'm attaching a piece of

the schematic from that project.  As you can see, the connections to the JTAG pins are not implied by

this version of BSCAN, but show up on the schematic, including the TDI input buffer to the user logic.

This particular BSCAN was used to capture USER commands to provide a few bits of control to the

design from an embedded micro that also configured the FPGA.

You're probably better off starting from scratch rather than trying to get anything out of this design...

-- Gabor

[benbenqiao]

Hi Gabor,

Thanks a lot ! We do appreciate all your help! Thank you so much.

Thanks

Ben