Virtex® Family FPGAs

[drodriguez]

Hello everybody,

I need to connect a DA converter (AD9744) with a Virtex 6 FPGA. I was thinking of using LVCMOS25 interface directly instead of using a level translator for the information bits coming from the FPGA into the DAC (less space). The DA characteristics are:

VILmax = 0.9 V, VIHmin = 2.1V

The problem is that I've found different specifications for Virtex 6 LVCMOS25 interface:

Virtex 6 DC and Switching Characteristics doc says that VOLmax = 0.4 V and  VOHmin = Vcco-0.4.(Table 1-17). With Vcco = 2.5 V I suppose it should work.

http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf

Virtex 6 Select IOResources doc says in page 36 that VOLmax = 0.4 V and VOHmin = 1.9 V (Table 7).

http://www.xilinx.com/support/documentation/user_guides/ug361.pdf

Which specification is correct?

Any suggestion?

Thanks in advance!

[gszakacs · Accepted solution]

If you look at table 1-7, it shows the Vcco for 2.5V CMOS as 2.3 volts minimum.  Then

Vcco - 0.4V would be 1.9V.  If you can trim your Vcco supply to be above 2.5V but below

2.625V (a pretty tight range), then you would be guaranteed 2.1V Voh.  On the other

hand for signals that don't need to drive the maximum rated current for the IO

standard, the Voh should be closer to Vcco than specified, going very nearly to

the Vcco rail when loaded with a few microamperes.  I imagine your DAC will

present a mostly capacitive load on the nets, so whether Voh goes above Vcco - 0.4V

will depend mostly on how much settling time you give the outputs before the clock

edge.

HTH,

Gabor

[mcgett]

There is a misunderstanding on the interpertation of the Virtex-6 datasheet.   The Voh(min) and Vol(max) numbers are the voltage points at which the Ioh and Iol currents are guaranteed.  As an example, if LVCMOS25 with a 12mA drive was used then at Voh of Vcco-0.4 (2.1V) 12mA of current would be able to be source by the output buffer.  If the load does not require 12mA then the output voltage will be higher, up to the VCCO level.