Virtex® Family FPGAs

[shamanth]

Hi,

I am currently working on ML561 board(Virtex5) and need to download HDL designs(behavioural, FSM, etc..) on the board to verify it in hardware. I am trying to find some tutorials or reference materials for the same but I can't seem to get anything substantial.

Can anyone please point me to some good reference material to understand the entire Embedded/FPGA design flow(possibly for ML561 using ISE10.1). I am trying really hard to understand the flow from various reference materials. Any help would be greatly appreciated.

Also, can HDL designs be ported and verified on the ML 561 board using ISE 10.1 alone or does it need EDK too?

Please help.

Thank you.

Shamanth S. Huddar

[sumi_u]

You can try reading the documentation provided by Xilinx along with ISE installation.

You will be able to find it in Xilinx/10.1/doc/usenglish/books folder in the drive you have installed Xilinx 10.1 design suite.

[shamanth]

Will check.

Thank you.

Shamanth.