Hi,
In the xapp878, there is a bit group called Lock Group. I want to know how to set the LockReg1, LockReg2, LockReg3 registers in VHDL. There seems no algorithm used to calculate these bits in the registers, and I have a difficulty understanding the following statement in the mmcm_drp_func.h:
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function [39:0] mmcm_lock_lookup
(
input [6:0] divide // Max divide is 64
);
reg [2559:0] lookup;
...
lookup = {
40'b00110_00110_1111101000_1111101001_0000000001,
...
};
// Set lookup_entry with the explicit bits from lookup with a part select
mmcm_lock_lookup = lookup[ ((64-divide)*40) +: 40]; --??
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what is the meaning of the "((64-divide)*40) +: 40"? And what is the VHDL equivalent ? Thanks!
PS: can the lookup table in the reference design be applied to the XC6VLX240T-FF1156 ?
