olufola wrote:
Hi bassman59,
I have already gone through the user and hardware configuration guides but the information provided about the use of the SMA clock inputs was not detailed enough. The fastest onboard (on the evaluation kit) clock is 200MHz . Should I interpret your answer to mean that I can use an external signal generator to clock the FPGA through the SMA inputs at a maximum frequency of 200MHz?
Thank you
The 200 MHz oscillator on board was probably chosen because it's "fast" and works with the kit's various demonstration designs.
The data sheets for the device indicate the maximum clock frequency allowed on the global clock buffers (unsurprisingly called Fmax in the data sheet). There are also maximum clock frequencies allowed for the I/O clock buffers and the PLL and DCM clock networks. All of these maximums are greater than the 200 MHz oscillator installed on the kit.
But, again, that's the maximum frequency supported by the clock networks, and it basically assumes a trivial design (toggling a single flip-flop or whatever). The actual maximum clock frequency is wholly determined by your design. If you have a lot of combinatorial logic then it's possible your maximum clock frequency will be less than the 200 MHz. You won't know until you go through the design exercise.
So if you constraint your design to run at 250 MHz, and it meets that timing constraint after running through the tools, then you can either replace the 200 MHz oscilator with one that works at 250 MHz, or you can provide a clock on the SMA connector or on any other available global clock input pin.
The SMA clock input itself isn't magic. The SMA connector has excellent signal integrity, with bandwidth in the GHz range, and there are several high-end signal generators capable of high-frequency clock outputs which use it.
Got it?
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Yes, I do this for a living.
