Virtex® Family FPGAs

[artanduraj]

What is the best way to share data between the Microblaze and the FPGA IP.

In essence the Microblaze will communicate with the user through RS232 and receive ceratin instructions, crunch some data based on the used info and create an array of 1000 elements. This array will need to be sent to the FPGA (somewhow) to perform analysis and drive a DAC.

[martinthompson · Accepted solution]

My vote would be FSL - it looks like a FIFO to both the SW in the microblaze, and to the IP core at the other end.

You could use the EDK wizards to do a PLB interface, but it sounds more like a "dump lots of data to IP core, and read it back when it's done" type activity.

Cheers,
Martin

[eilert]

Hi,

FSL would be one way.

An SRAM Controller to some dual port RAM another.

You can put it in some free address range and fill it with your data and the IP-Core can directly work on it.

Have a nice synthesis

  Eilert

[artanduraj]

Thank you for the feedback. I think I got what I need.