bassman59 wrote:
rmarcel wrote:
If in Virtex-5 we have 6-LUT with the 2 outputs O6 and O5, and is possible to have 2 different function of 5 inputs each.
How implement 2 multiplexer 2:1 in one 6-LUT?
signal muxout : std_logic;
signal foo : std_logic;
signal bar : std_logic;
signal select : std_logic;
....
muxout <= foo when select = '1' else bar;
You're welcome.
More likely that the following would infer 2 multiplexers like what the OP wants:
signal muxout : std_logic_logic(1 downto 0);
signal foo : std_logic_logic(1 downto 0);
signal bar : std_logic_logic(1 downto 0);
signal select : std_logic;
....
muxout <= foo when select = '1' else bar;
Except that the the multiplexers aren't independent, which may be what (s)he wants. Why one would really care in a normal industrial design is another matter.
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"If it don't work in simulation, it won't work on the board."
