03-01-2010 06:45 PM
I'm designing an LPDDR2 SDRAM memory interface controller for a Virtex-6 FPGA based on the DDR3 interface controller provided by MIG 3.3.
The memory interface signals need a 1.2V IOStandard. For the single-ended signals, either LVCMOS12 or HSTL_I_12 IOStandard can be used. The problem is on the differential (CK and DQS) signals, there is no differential 1.2V IOStandard supported. Is there any workaround for this issue? Is it possible to configure the logic to a 1.5V IOStandard (for example DIFF_SSTL15) and tweak VCCO and VREF in such a way to get the IOB lines within the desired 1.2V swing?
03-02-2010 08:13 AM
I would do as you suggest: use the nearest equivalent (1.5v differential input). There is no Vref to set. Use 1.2 volts on the Vcco.
If you have the tools, you can request the encrypted hspice models, and set your Vcco to 1.2 volts, and see exactly what the performance differences will be (ie delay, rise, fall) by simulating the IO at 1.5 volts, and then again at 1.2 volts.
If you don't have hspice, then you will have to do this the hard way: characterize the IO for this non-standard IO yourself. This means that you will have to operate the IO at the highest temperature allowed by the device (85C for commercial, 100C for industrial), at the lowest Vcco supply, perhaps use 1.1 volts (more than a -5% change).
If it works under these conditions, then you need to find where it doesn't work any longer (continue to drop the Vcco). At some point, you are either comfortable with the use under these conditions, or not. Xilinx only gaurantees the numbers in the data sheet, so we can not stand behind this use, you have to be confident it will work in your application.
Personally, I would go with the hspice route, as the cost of the hspice license is trivial when compared with the risks of not getting the characterization done right. In hspice, you can choose the slowest process corner, lowest Vcco, and highest temperature, and since the hspice model IS the IO (we use hspice to genrate the IBIS models, and thus these become part of the specifications), what you see is what you will get.
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