Virtex® Family FPGAs

[rhayne]

Good day.

I have an ML507 board which has Virtex 5. I want to test my design at a higher frequency(overclock) than what is used by the FPGA(which is 100MHz). Is there a way to do that in HDL? If not, the use of external will be inevitable. What components/devices/chips can I use for that purpose? 

Thank you.

[jschimek]

In HDL you have access to DCMs and PLLs which should allow you to increase CLK frequency to the internal logic.  The User Guide covers usage:

http://www.xilinx.com/support/documentation/user_guides/ug190.pdf

Regards,

Jon

[austin]

r,

As suggested, use the DFS feature of the DCM, so you may generate 32/31 of the clock, 16/15, 8/7, 4/3, 3/2, etc. effectively going to higher and higher frequencies.

Generally, late in the manufacture of any parts, most devices are yielding at -3 (process is tuned to get best performance/power and yields get very very good).  So you should be able to run things up to 30% faster, but there are no gaurantees other than the speed grade marked on the part.

[rhayne]

Thanks for the quick response.

I may be able to use that, but is it possible to have the increase in clock to about 200MHz and above?

[sushantm]

may be able to use that, but is it possible to have the increase in clock to about 200MHz and above?

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For 200 Mhz & above you can check with available differential Frequency on board.

Or else you can generate the required single ended/differential freq using DCM.