Virtex® Family FPGAs

[waris.mohammad]

Hi guys,

                I am working with V5 LX30T device i have instantiated a DCM_PLL block using cre generator. Synthesis and Placement is fine but during route it failed to rouote 5 nets all related to this block . i am attaching the p&r  report. plz have a look. 

[sushantm]

am working with V5 LX30T device i have instantiated a DCM_PLL block using cre generator. Synthesis and Placement is fine but during route it failed to rouote 5 nets all related to this block . i am attaching the p&r  report. plz have a look.

---

With ref to you par report it seems the tool is having an issue with placements.

The reasons maybe

1.you might had provided unmatched placement constraints.

--> Put the specific constraints for DCM I/O & loc the DCM manually(if the tool is unable to do (automatic)) to specific location refer device datasheet & DCM user guide for details.

2.If you are cascading two DCM's follow the proper rules or else avoid cascading of DCM if not necessary.

3.Check if there is proper insertion of BUFG's & IBUF wherever required viceversa.

[mcgett]

Without seeing the code for the ensign it isn't possible to determine what is wrong for the error messages in the PAR report file.

[waris.mohammad]

Thanks for your replies.

is it sufficient to add the top level module code snippet which contains DCM instantiation?

I am using PLL to clean the clock and then DCM to do frequency synthesis. It is same as the example given in Fig-2-14 of V5 userguide (ug190).

Shall i also add the code generated for this block from Core generator.

regards

waris

[mcgett]

You need to post enough code that recreates the problem.

[waris.mohammad]

Here are the two files which may recreate the problem .

[waris.mohammad]

here is the PLLto DCM file.

[waris.mohammad]

Dear mcgett,

                         Kindly have alook at the code. PAR failes for this code snippet also.

[sushantm · Accepted solution]

With reference to your code.

While Implementations it gives error as

ERROR:LIT:540 - PLL_ADV symbol "physical_group_CLKOUTDCM0_CLKIN/PLL_ADV_INST"
   has its CLKOUTDCM output bus driving a load that is not a DCM. This will
   result in an unroutable design. Please modify the design so that the
   PLL_ADV's CLKOUTDCM output bus only drives DCM loads and use the PLL_ADV's
   CLKOUT output bus to drive non-DCM loads.

So your CLKOUTDCM0_CLKIN of PLL_ADV_INST shouldnot drive the load which is not a dcm.

I just tried to remove the error as follows.

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1
--  \   \         Application : xaw2vhdl
--  /   /         Filename : plltodcm_v5_coregen.vhd
-- /___/   /\     Timestamp : 02/09/2011 10:19:34
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: xaw2vhdl-st C:\Documents and Settings\QA\My Documents\plltodcm_v5_coregen.xaw C:\Documents and Settings\QA\My Documents\plltodcm_v5_coregen
--Design Name: plltodcm_v5_coregen
--Device: xc5vlx30t-ff665-3
--
-- Module plltodcm_v5_coregen
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.058 UI
-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.146 ns
-- For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUTDCM0 = 0.114 ns

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity plltodcm_v5_coregen is
   port ( CLKIN1_IN       : in    std_logic; 
          RST_IN          : in    std_logic; 
          CLK0_OUT        : out   std_logic; 
          LOCKED_OUT      : out   std_logic; 
          U1_CLKFX_OUT    : out   std_logic; 
          U1_CLKFX180_OUT : out   std_logic; 
          U1_CLK2X_OUT    : out   std_logic; 
          U1_CLK90_OUT    : out   std_logic; 
          U1_CLK180_OUT   : out   std_logic; 
          U1_CLK270_OUT   : out   std_logic);
end plltodcm_v5_coregen;

architecture BEHAVIORAL of plltodcm_v5_coregen is
   signal CLKFBDCM_CLKFBIN : std_logic;
   signal CLKFB_IN         : std_logic;
   signal CLKIN1_IBUFG     : std_logic;
   signal CLKOUTDCM0_CLKIN : std_logic;
   signal CLK0_BUF         : std_logic;
   signal DCM_RST_IN       : std_logic;
   signal FDS_Q_OUT        : std_logic;
   signal FD1_Q_OUT        : std_logic;
   signal FD2_Q_OUT        : std_logic;
   signal FD3_Q_OUT        : std_logic;
   signal GND_BIT          : std_logic;
   signal GND_BUS_5        : std_logic_vector (4 downto 0);
   signal GND_BUS_7        : std_logic_vector (6 downto 0);
   signal GND_BUS_16       : std_logic_vector (15 downto 0);
   signal LOCKED_INV_IN    : std_logic;
   signal LOCKED_INV_RST   : std_logic;
   signal OR3_O_OUT        : std_logic;
   signal U1_CLKFX_BUF     : std_logic;
   signal U1_CLKFX180_BUF  : std_logic;
   signal U1_CLK2X_BUF     : std_logic;
   signal U1_CLK90_BUF     : std_logic;
   signal U1_CLK180_BUF    : std_logic;
   signal U1_CLK270_BUF    : std_logic;
   signal VCC_BIT          : std_logic;
   signal CLKOUTDCM0_CLKIN_test          : std_logic;
begin
   GND_BIT <= '0';
   GND_BUS_5(4 downto 0) <= "00000";
   GND_BUS_7(6 downto 0) <= "0000000";
   GND_BUS_16(15 downto 0) <= "0000000000000000";
   VCC_BIT <= '1';
   CLK0_OUT <= CLKFB_IN;
   CLKIN1_IBUFG_INST : IBUFG
      port map (I=>CLKIN1_IN,
                O=>CLKIN1_IBUFG);
   
	

   CLK0_BUFG_INST : BUFG
      port map (I=>CLK0_BUF,
                O=>CLKFB_IN);
   
   DCM_ADV_INST : DCM_ADV
   generic map( CLK_FEEDBACK => "1X",
            CLKDV_DIVIDE => 2.0,
            CLKFX_DIVIDE => 1,
            CLKFX_MULTIPLY => 8,---initially 4
            CLKIN_DIVIDE_BY_2 => FALSE,
            CLKIN_PERIOD => 20.000,----50Mhz from clkgen_o signal
            CLKOUT_PHASE_SHIFT => "NONE",
            DCM_AUTOCALIBRATION => TRUE,
            DCM_PERFORMANCE_MODE => "MAX_SPEED",
            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE => "HIGH",
            DLL_FREQUENCY_MODE => "LOW",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF => x"F0F0",
            PHASE_SHIFT => 0,
            STARTUP_WAIT => TRUE,
            SIM_DEVICE => "VIRTEX5")
      port map (CLKFB=>CLKFB_IN,
--                CLKIN=>CLKOUTDCM0_CLKIN,
                CLKIN=>CLKOUTDCM0_CLKIN_test,
                DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
                DCLK=>GND_BIT,
                DEN=>GND_BIT,
                DI(15 downto 0)=>GND_BUS_16(15 downto 0),
                DWE=>GND_BIT,
                PSCLK=>GND_BIT,
                PSEN=>GND_BIT,
                PSINCDEC=>GND_BIT,
                RST=>DCM_RST_IN,
                CLKDV=>open,
                CLKFX=>U1_CLKFX_BUF,
                CLKFX180=>U1_CLKFX180_BUF,
                CLK0=>CLK0_BUF,
                CLK2X=>U1_CLK2X_BUF,
                CLK2X180=>open,
                CLK90=>U1_CLK90_BUF,
                CLK180=>U1_CLK180_BUF,
                CLK270=>U1_CLK270_BUF,
                DO=>open,
                DRDY=>open,
                LOCKED=>LOCKED_OUT,
                PSDONE=>open);
   
--   FDS_INST : FDS
--      port map (C=>CLKOUTDCM0_CLKIN,
--                D=>GND_BIT,
--                S=>GND_BIT,
--                Q=>FDS_Q_OUT);
--   
--   FD1_INST : FD
--      port map (C=>CLKOUTDCM0_CLKIN,
--                D=>FDS_Q_OUT,
--                Q=>FD1_Q_OUT);
--   
--   FD2_INST : FD
--      port map (C=>CLKOUTDCM0_CLKIN,
--                D=>FD1_Q_OUT,
--                Q=>FD2_Q_OUT);
--   
--   FD3_INST : FD
--      port map (C=>CLKOUTDCM0_CLKIN,
--                D=>FD2_Q_OUT,
--                Q=>FD3_Q_OUT);
--   
--   OR2_INST : OR2
--      port map (I0=>LOCKED_INV_RST,
--                I1=>OR3_O_OUT,
--                O=>DCM_RST_IN);
--   
--   OR3_INST : OR3
--      port map (I0=>FD3_Q_OUT,
--                I1=>FD2_Q_OUT,
--                I2=>FD1_Q_OUT,
--                O=>OR3_O_OUT);
   
   PLL_ADV_INST : PLL_ADV
   generic map( BANDWIDTH => "OPTIMIZED",
            CLKIN1_PERIOD => 20.000,
            CLKIN2_PERIOD => 20.000,
            CLKOUT0_DIVIDE => 8,
            CLKOUT1_DIVIDE => 8,
            CLKOUT2_DIVIDE => 8,
            CLKOUT3_DIVIDE => 8,
            CLKOUT4_DIVIDE => 8,
            CLKOUT5_DIVIDE => 8,
            CLKOUT0_PHASE => 0.000,
            CLKOUT1_PHASE => 0.000,
            CLKOUT2_PHASE => 0.000,
            CLKOUT3_PHASE => 0.000,
            CLKOUT4_PHASE => 0.000,
            CLKOUT5_PHASE => 0.000,
            CLKOUT0_DUTY_CYCLE => 0.500,
            CLKOUT1_DUTY_CYCLE => 0.500,
            CLKOUT2_DUTY_CYCLE => 0.500,
            CLKOUT3_DUTY_CYCLE => 0.500,
            CLKOUT4_DUTY_CYCLE => 0.500,
            CLKOUT5_DUTY_CYCLE => 0.500,
            COMPENSATION => "PLL2DCM",
            DIVCLK_DIVIDE => 1,
            CLKFBOUT_MULT => 8,
            CLKFBOUT_PHASE => 0.0,
            REF_JITTER => 0.000000)
      port map (CLKFBIN=>CLKFBDCM_CLKFBIN,
                CLKINSEL=>VCC_BIT,
                CLKIN1=>CLKIN1_IBUFG,
                CLKIN2=>GND_BIT,
                DADDR(4 downto 0)=>GND_BUS_5(4 downto 0),
                DCLK=>GND_BIT,
                DEN=>GND_BIT,
                DI(15 downto 0)=>GND_BUS_16(15 downto 0),
                DWE=>GND_BIT,
                REL=>GND_BIT,
                RST=>RST_IN,
--                CLKFBDCM=>CLKFBDCM_CLKFBIN,
                CLKFBDCM=>open,
                CLKFBOUT=>open,
--                CLKFBOUT=>CLKFBDCM_CLKFBIN,
                CLKOUTDCM0=>CLKOUTDCM0_CLKIN,
                CLKOUTDCM1=>open,
                CLKOUTDCM2=>open,
                CLKOUTDCM3=>open,
                CLKOUTDCM4=>open,
                CLKOUTDCM5=>open,
                CLKOUT0=>open,
                CLKOUT1=>open,
                CLKOUT2=>open,
                CLKOUT3=>open,
                CLKOUT4=>open,
                CLKOUT5=>open,
                DO=>open,
                DRDY=>open,
                LOCKED=>LOCKED_INV_IN);
   
   U1_CLKFX_BUFG_INST : BUFG
      port map (I=>U1_CLKFX_BUF,
                O=>U1_CLKFX_OUT);
   
   U1_CLKFX180_BUFG_INST : BUFG
      port map (I=>U1_CLKFX180_BUF,
                O=>U1_CLKFX180_OUT);
   
   U1_CLK2X_BUFG_INST : BUFG
      port map (I=>U1_CLK2X_BUF,
                O=>U1_CLK2X_OUT);
   
   U1_CLK90_BUFG_INST : BUFG
      port map (I=>U1_CLK90_BUF,
                O=>U1_CLK90_OUT);
   
   U1_CLK180_BUFG_INST : BUFG
      port map (I=>U1_CLK180_BUF,
                O=>U1_CLK180_OUT);
   
   U1_CLK270_BUFG_INST : BUFG
      port map (I=>U1_CLK270_BUF,
                O=>U1_CLK270_OUT);
   
   U1_INV_INST : INV
      port map (I=>LOCKED_INV_IN,
                O=>LOCKED_INV_RST);
   
end BEHAVIORAL;

You can consider the above as workaround and do the changes into your code according to your requirement.

Above code runs through implementation process & routes the design with all nets without any issues.

[waris.mohammad]

Dear sushantam ,

                                  Thanks for showing a workaround for the problem.

This code was generated by the coregenerator so i simply copied and pasted in my design. Does this mean the coregen is not reliable ?