Virtex® Family FPGAs

[mjholmes99]

Using ISE 12.2. I have the PERIOD constraint on my clock in the VHDL like so:

    attribute period: string;
    attribute period of clock:signal is "200 MHz";

where "clock" is the output of the BUFG.

When I reach place and route I see the "design has no timing constraints" warning. Any idea where the PERIOD constraint is getting dropped? Is there an XST setting I need to set? Tie the constraint to the input pin or the BUFG itself?

All other constraints in my VHDL file, such as LOC and IOSTANDARDs, work fine. PERIOD is the only on not making it between synthesis and the NGDBuild, MAP and PAR sequence.

It works if I plop PERIOD in a UCF file, but I'd like having that stuff in the VHDL top level. Call it a quirk. ;-) I'll do it if I have to, but thought I'd ask. There's got to be some dumb thing I'm missing or check box I'm not setting.

[rcingham]

I presume that it also doesn't work with
attribute period of clock:signal is "5.0 ns";

Reading the section on "XST Timing Constraints" in UG627 suggests that it isn't supported. Shame, really. I would like to put False Path attributes in my HDL, but have had to put them in the UCF.

[rockel]

I assume you are using XST as your synthesis tool... if so, verify in the Synthesize "Process Properties" --> "Synthesis Options" tab that you have the "Write Timing Constraints" enabled (i.e. box is checked).  This option is disabled by default.  "Write Timing Constraints" will guide XST to place timing constraints in the NGC file for NGDBuild to read during implementation.