Virtex® Family FPGAs

[hg81]

Should I use Planahead or just assign pin continuously in a bank of Virtex 6 to connect with DDR3?

Thanks.

[awillen]

Well, are you using an existing board or are you designing a PCB?

Adrian

[jschmitz]

I recommend that you use the MIG tool found in CORE Generator (Memories & Storage Elements / Memory Interface Generators).

[stuartnthomson]

I'd agree that using the MIG to generate the necessary files is the best solution. One of the outputs is a .ucf file which contains pin out data.

That's much easier than trying to do it manually within PlanAhead and it's more likely to work (and it's also a bit quicker).

You can then import the .csv file into PlanAhead and that will show you pictorially which banks etc are used.

You can also export this from PlanAhead as a .csv to Excel if required. Note that any additional PlanAhead import operations overwrite existing data so any mods (e.g.. another interface, more pins) have to be added manually either by hand within PlanAhead, or within Excel and re-imported.

[ljgkd]

I use MIG generate DDR3 constrains file(ucf),but when  verified this UCF,I encounted ERROR messages as follows.

 This is the message format for resynchronization clock (BUFR) constraints:
ERROR: The BUFR Constraint for the FPGA column '1' is not provided
in the UCF or Constraint provided for this column is not valid.
Following is(are) valid BUFR constraints.
AJ41 - X0Y143.
AD36 - X0Y141.
AF36 - X0Y139.
AD37 - X0Y137.
ERROR: The BUFR Constraint for the FPGA column '1' is not provided
in the UCF or Constraint provided for this column is not valid.
Following is (are) valid BUFR constraints.
AT6 - X2Y143.
AT9 - X2Y141.
AV6 - X2Y139.
AW7 - X2Y137.

[robinliuy]

Check this AR:http://tskb/Articles/41444.aspx
This is an known issue and will be fixed in MIG3.8 (ISE13.2). You can ignore it.