Virtex® Family FPGAs

[timothybean]

Hello,

I have been having problems copiling my design. There seems to be something wrong with GND... That is all I can figure out so far. I have been disconnecting grounds to get the problems to go away:

ERROR:NgdBuild:455 - logical net 'N0' has multiple driver(s):
     pin G on block XST_GND with type GND,
     pin PAD on block N0 with type PAD

I do not have XST_GND in my project nor N0.

When I put some of my grounds in I get something like this:

 Checking expanded design ...
ERROR:NgdBuild:455 - logical net 'XLXI_1/XLXN_282' has multiple driver(s):
     pin G on block XLXI_1/XLXI_141 with type GND,
     pin PAD on block XLXI_1/XLXN_282 with type PAD
ERROR:NgdBuild:924 - input pad net 'XLXI_1/XLXN_282' is driving non-buffer
   primitives:
     pin G on block XLXI_1/XLXI_141 with type GND,
     pin CLR on block XLXI_29/XLXI_1/I_36_35 with type FDC,
     pin CLR on block XLXI_29/XLXI_2/I_Q3/I_36_35 with type FDCE,
     pin CLR on block XLXI_29/XLXI_2/I_Q2/I_36_35 with type FDCE,
     pin CLR on block XLXI_29/XLXI_2/I_Q1/I_36_35 with type FDCE,
     pin CLR on block XLXI_29/XLXI_2/I_Q0/I_36_35 with type FDCE,
     pin CLR on block XLXI_29/XLXI_3/I_Q1/I_36_35 with type FDCE,
     pin CLR on block XLXI_29/XLXI_3/I_Q0/I_36_35 with type FDCE,
     pin CLR on block XLXI_30/XLXI_3/I_Q3/I_36_35 with type FDCE,
     pin CLR on block XLXI_30/XLXI_3/I_Q2/I_36_35 with type FDCE,
     pin CLR on block XLXI_30/XLXI_3/I_Q1/I_36_35 with type FDCE,
     pin CLR on block XLXI_30/XLXI_3/I_Q0/I_36_35 with type FDCE
WARNING:NgdBuild:478 - clock net XLXN_211 with clock driver XLXI_75 drives no
   clock pins

XLXN_282 is a wire that is connected between ground symbol and a CLKDLE RST pin.

XLXI_29/XLXI_2/I_Q3/I_36_35 with type FDCE doesn't even have a ground pin going to it as far as I can see.

This only happens when I compile it as the or under the top level of the project. If I just have it as a sub module it compiles and simulates fine. PLEASE help me. 

I am using ISE 10.1 and a Virtex-II 

Thanks

[mcgett]

There error messages imply that you have an input port, either N0 or XLXN_282, that is defined or assigned to ground. 

I would suggest that you go through your synthesis report or log file and check all of the warnings.

[timothybean]

Thanks for the suggestion. I have ground going to a DCM RST pin. I need to pull it low. Is this not how I would do it?

Thanks

[mcgett]

If you need a ground in your design then you assign it to a logic 0.  Logic 0 and 1 states are generated internally in the FPGA and not from external pins.

[timothybean]

Sorry for being a little nieve, I am still learning the software tools. I find them very hard to use. So, if I need it to be add the ground, ie. pulling RST low on DCM, Do I use a constant and set it to 0? I am doing this graphically.Also, how would i locate N0 net? I do a search and it doesn't find anything....

Thanks

Tim

[mcgett]

A Virtex design using schematic entry?  I'm a bit surprised by this as the other warning messages indicated that you were synthesizing the design.

Schematic entry would involve adding the GND symbol and connecting the single output pin to the DCM RST input pin.

PULLDOWN or PULLUP symbol should only be attached to the input of an IBUF or the output of an OBUFT.

[timothybean]

Ok,

Thanks for the replies! I found the problem, although the error messages really didn't point me towards the problem, and that is what was screwing me up. I accidentally put a IFD in place of an FD. Don't know how I did this, and didn't notice it at first. But, once I replaced it, all is well.

Thanks

Tim