Hi,
I took the ML506 CoSimulation files and modified them for the ML507. It works for JTAG, then at least you can start to play !!!
The Zipped file must be uncompressed in "..\Xilinx\13.4\ISE_DS\ISE\sysgen\plugins\compilation\Hardware Co-Simulation" diredctory.
Ethernet is still problemantic. Some modifications to the .UCF file for both Point-to-Point and Network based Co-Simulation are necessary. When running the xflow, timing problems occurs with "ethernet_phy_rx_clk" signal:
ERROR:Place:872 - Delay element
"ehwc_iface/u_phy_iface/u_clk_gen/idelay_based_rx_clk_gen.u_rx_clk_gen/delay_ gmii_rx_clk" has been placed at IODELAY_X1Y219 due to the following location constraint on component "ethernet_phy_rx_clk":
COMP "ethernet_phy_rx_clk" LOCATE = SITE "H17" LEVEL 1
However, the delay controller that calibrates this delay element has not been used. Please instantiate a delay controller and apply appropriate location constraint, or instantiate one delay controller for the design with out any location constraint. Please refer to the usage document to use the controller efficiently.
If somebody has knownledge, please help us !!!
Thanks in advance,
