Virtex® Family FPGAs

[tklau]

Implementing XAPP860 (16-Channel, DDR LVDS Interface with Real-Time Window Monitoring) on Virtex-5 (XC5VLX50T-1FFG1136, on ML505), and encounter with an error during mapping:

LIT:516 - BUFIO symbol "RX_CLK_BUFIO" (output signal=RXCLK_OBUF) cannot drive an OBUF(DS) or OBUFT(DS) as this will create an unroutable situation. Please modify your design.

Here are the implementation files.

Does anyone have similar problems?

[eteam00]

In general, Xilinx FPGAs have two separate on-chip interconnect networks, for normal logic signals and for clocks, respectively.  The clock interconnect is designed for low skew, and normal logic interconnect is designed for maximum flexibility.  The special needs and interests of clock interconnect necessarily limit its flexibility -- the clock distribution network does not connect to the normal logic signal network.

The inputs to OBUFDS and OBUFT cannot be directly driven from the clock interconnect driven by a BUFIO clock buffer.  If you notice in xapp860, Figure 5, the LVDSEXT_25 buffer in the bottom right corner is not directly driven by the BUFIO clock buffer.  It is indirectly driven through an ODDR block.  This is a common circuit application in Xilinx designs, also used for 'clock forwarding' in designs which generate source-synchronous data+clock outputs.

-- Bob Elkind

[tklau]

In Xilinx's design (XAPP860), RX_CLK_BUFIO is driven by BUFIO.

To work around this LIT:516 error, I should make some changes so that RX_CLK_BUFIO is driven by an ODDR block?

[eteam00]

In Xilinx's design (XAPP860), RX_CLK_BUFIO is driven by BUFIO.

To work around this LIT:516 error, I should make some changes so that RX_CLK_BUFIO is driven by an ODDR block?

No.

See XAPP860 Figure 8.  There is no OBUFDS in this diagram.  Is the OBUFDS for the RX_CLK in the original XAPP860 example code, or is this an addition which you have made?  In either case, BUFIO does not directly drive OBUFDS.  BUFIO can drive ODDR, and ODDR can directly drive OBUFDS (see XAPP860, bottom of Figure 5).

-- Bob Elkind

[eteam00]

In Xilinx's design (XAPP860), RX_CLK_BUFIO is driven by BUFIO.

To work around this LIT:516 error, I should make some changes so that RX_CLK_BUFIO is driven by an ODDR block?

No.

See XAPP860 Figure 8.  There is no OBUFDS in this diagram.  Is the OBUFDS for the RX_CLK in the original XAPP860 example code, or is this an addition which you have made?  In either case, BUFIO does not directly drive OBUFDS.  BUFIO can drive ODDR, and ODDR can directly drive OBUFDS (see XAPP860, bottom of Figure 5).

-- Bob Elkind

[tklau]

No any modification on their sample codes (XAPP860), and got an error LIT:516 on RX_CLK_BUFIO during mapping.

It's how they put the RX_CLK in DDR_6TO1_16CHAN_RT_RX.v,

BUFIO RX_CLK_BUFIO
(
.O(RXCLK), 
.I(CLOCK_RX_ISERDES_OUT)
);

[eteam00 · Accepted solution]

No any modification on their sample codes (XAPP860), and got an error LIT:516 on RX_CLK_BUFIO during mapping.

If you are using file DDR_6TO1_16CHAN_RT_RX.v as the top-level module, then RXCLK should be removed from the module port list.  The BUFIO which drives this signal is correct, as this is the IO clock for the ISERDES blocks (and more).

The file DDR_6TO1_16CHAN_RT_TX.v has a good example of the correct implementation of clock forwarding to an output pin:

//FORWARDED CLOCK    
ODDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT(1'b0),
    .SRTYPE("ASYNC")
) ODDR_TX_CLOCK
    (
    .Q(TX_CLOCK_PREBUF),
    .C(TXCLK),
    .CE(1'b1),
    .D1(1'b1),
    .D2(1'b0),
    .R(1'b0),
    .S(1'b0)
    );

//FORWARDED CLOCK OUTPUT BUFFER
OBUFDS_LVDSEXT_25 OBUFDS_TX_CLOCK  // try OBUFDS instead of OBUFDS_LVDSEXT_25
    (
    .O(CLOCK_TX_P),
    .OB(CLOCK_TX_N),
    .I(TX_CLOCK_PREBUF)
    );

Note:  I cannot find any reference to a OBUFDS_LVDSEXT_25 Virtex-5 primitive.  Perhaps there is a missing source code file which defined a OBUFDS_LVDSEXT_25 module.  Or maybe OBUFDS_LVDSEXT_25 simply maps to OBUFDS.

-- Bob Elkind

[tklau]

Thank you very much!