Virtex® Family FPGAs

[richard.cyril.38]

Hello (sorry for my  bad english, i'm french ).

I realize now for my university, a little project on a virtex 5 (LX110T 1136).
I made several tutorials (lab ressorces).

So I implented a simple architecture (micrbloaze ,icap and sram connected on my PLB bus with a GPIO port to control a LCD module).
Everything works properly, I'm able to read, rewrite the FPGA configuration (via ICAP), to correct it, etc. ...

So I based on the lab ressource icap_processor_lab (shift of LEDs).
But then, when I sent some partial bitstream, the LEDs remain frozen (Or is behaving strangely).

For example, if I send the bitstream to shift the LEDs on the left followed by the bitstream to shift leds to right it works, if I send an other bitstream and send back the bistream to shift the leds to right, they remain frozen.
I started my project several times without finding a solution.

I must then send a full bitstream to the fpga t reconfigure leds correctly.

I just added SRAM (new addition to the TP),
I replaced the DCM by a clock generator.
I have added the flag "-g readback" in bitgen and defined "keep hierarchy: yes" in ISE.

I am a beginner and am a bit lost ^^'.

Maybe
If you have some ideas.

Thank you very much.

PS: I tested to send bistream from JTAG or read from the compact flash, same result).

All fullbistream work.

[chenweit]

Richard,

The main difference between PR bitstream and full is that PR bitstream doesn't issue GRESTORE. That means, if your PR code relies on initilization value, you do not get them. All registers that are critical to your design must be reset by the user. There is plan for this to be automated, but you're responsible for now.

For debugging, I'll recommend adding in chipscope to your static region and probe the PR region if you can afford the additional logic.

Regards,

Wei

[richard.cyril.38]

Thank you very much for you response.
So, i need to apply a reset on my reconfigurable module.

For example, on my reconfigurable module (controlled by led_control from Xilinx labs), there is a reset signal.

When should I apply the reset? during partial reconfiguration? after?

And how (how can i control the reset input ? from my microblaze application?, ...).

And how can i detect the end of partial cofniguration from ICAP?

Thank a lot for your help.

[richard.cyril.38 · Accepted solution]

Hello,

i just solve my problem.

I changed size of the ICAP FIFO in XPS (Read/Write) from 256 (I had previously changed in the begging of my project) to 128, and no more problem.

All bitstream are OK.

i tested it with default setting (for FIFO size) and all is OK.

So, why with a size larger of 256 i have this bug, i don't know.

I also added a GPIO port (XPS), and i connected it to my reset signal.

Now i am able to control the reset of my Reconfigurable module from Microblaze.

^^ 

Thank you very much for your help.