Virtex® Family FPGAs

[xilinx_user9]

Hello,

There's no information of write mode for RAMB36SDP (either in User Guide or in "Virtex-5 Libraries Guide for HDL Designs"). It seems to be Read_First or no_change ?

Moreover, there's no "WRITE_MODE" attribute ! I'm waiting for having "Write first" memory behaviour (like the default behaviour of others memories) but simulation don't show that.

[yijing]

RAMB36SDP is a simple dual port memory. One port is for writing and the other for reading. It is meaningless to set write_mode of portA or portB since portA has only writing control logic and portB has only reading logic.

Y.J. 

[xilinx_user9]

Hello Yijing,

I'm disagree with you : I know that RAMB36SDP is a simple dual port memory but Write_Mode attribute controls outputs after writing so it's not meaningless. And in this case why the RAMB16_S36 single-port memory has a write_mode attribute ? And when I replace one RAB36SDP with two RAMB16_S36 the output behaviour is not the same. So I maintain there's a problem or a bug with RAM36SDP.

Regards.

[yijing]

Hi,

Write_mode will affect output of BRAM. For RAMB36DSP, there is no output port (DO) of portA so write_mode can be ignored for portA. Meanwhile, there is no input port (DI) of partB for RAMB36DSP, so write_mode for portB, I think, can be ignored too.

[xilinx_user9]

Hi,

Please look at RAMB16_S36 component (in unisim_VCOMP.vhd) there's only one port (like the RAMB36SDP) and there's a WRITE_MODE attribute. Please look at Virtex-5 User Guide, p115 where they talk about Write_Mode attribute : they don't talk about port A or port B but the behaviour of output when you write into the memory: this is the problem/bugI arise, for RAM36SDP it seems to be READ_FIRST and I would to have WRITE_FIRST mode.

Regards.

[yijing]

If you suspect this is a bug, please open a webcase on www.xilinx.com/support, along with your project. More help can be got there.

Regards

Y.J.

[xilinx_user9]

Hi,

Thanks for your support. I will open a Webcase when I'll be back from vacation.

Regards.

[xilinx_user9 · Accepted solution]

I've found the solution in Virtex-5 User Guide, p115 : "For the simple dual port block RAM, the Write mode is always READ_FIRST". Event if I don't understand  this limitation, this answers my question...

Note : simple dual port block RAM are RAMB18SDP and RAMB36SDP.

[shixianbai]

my use the xilinx v2p board ,i have read the document about mig007 and download it ,but now i do not how to use mig007 realizing  DDR SDRAM.There is mig007 among the three modes of the Tool, Pin is editor, solutions, but I don't know whether mig007 in all three of the need to install, especially the Pin, I really don't know editor, and how such after setting the files can be used to generate simulation and down to the board of mig007 generated by not, what can realize the function.

thank you!!!