Virtex® Family FPGAs

[pixie_sunky]

Hi everyone

I have searched the Regional clock resource on Virtex-5 board and it says one BUFR can only drive up to 3 clock regions.

I have a interesting example that I use one BUFR to drive a design implemed over 3 clock regions, for examples 5 clock regions in total. When I finished implementation, it works correcting and meet the timing performance. I use the FPGA editor to open the implemented design and have a look at the clock resource. I foud the clock reource after the BUFR can only cover 3 clock regions while the rest (another 2 clock regions left) cannot be covered by the regional clock resource.

My question are: is this design (one BUFR to drive the design over 3 clock regions) available??

                               so, for the rest clock regions (regional clock resource didn't cover), what kind of clock resource is used by the design to perform the implementation.

Many Thanks for that.

[avrumw]

In the V5, a BUFR can drive 3 regions total - the region that it is in, the one above, and the one below.

As for how the clock is routed outside the 3 regions, you would need to look at FPGA Editor to find out. It probably used locally routed clocks, where the clock is routed into "general routing" - these can have large clock insertion and clock skews (which can lead to all sorts of nasty timing problems).

Avrum

[pixie_sunky]

Thanks for your reply

I will have a look the design carefully. I guess the clock resource of my design would be a mixed one: regional clock and local clock.

Cheers

[pixie_sunky]

Hi Here is the design I use BUFR on Virtex-5 lx 110t device.  The design is implemented within 3adjacent clock regions.

But I am not quite sure if the design uses regional clock resource correctly (cause it looks like using local clock routing)??

Does some have the experience and help me have a look at it??

Here is the implemented design on FPGA editior 

Cheers

[ywu]

The resolution of the attached picture is not so good. Can you post the actual NCD?

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pixie_sunky wrote:

Hi Here is the design I use BUFR on Virtex-5 lx 110t device.  The design is implemented within 3adjacent clock regions.

But I am not quite sure if the design uses regional clock resource correctly (cause it looks like using local clock routing)??

Does some have the experience and help me have a look at it??

Here is the implemented design on FPGA editior 

Cheers

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