05-13-2010 02:56 AM
I am implementing a 240-bit shift register in 2vp30 through ISE 8.1i. It starts working from third clock cycle. in first 2 clock cycles nothing is stored in register r3. I have implemented my code with different ways but problem is still there. please help me. Simulation is attached.
output [239:0] r1,r2,r3;
r1 <= r2;
r2 <= r3;
r3 <= in;
05-13-2010 08:30 AM
You have implemented 3 stage shift register that is 240 bits wide, so it takes 3 clock cycles for the original data to propogate through the chain.
What were you expecting to happen?
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