Virtex® Family FPGAs

[anch_83]

Hi All,

I am implementing a 240-bit shift register in 2vp30 through ISE 8.1i. It starts working from third clock cycle. in first 2 clock cycles nothing is stored in register r3.  I have implemented my code with different ways but problem is still there. please help me. Simulation is attached.

module shift_reg(in,r1,r2,r3,clk);
input [239:0]in;
output [239:0] r1,r2,r3;
reg [239:0]r1,r2,r3;
input clk;
always@(posedge clk)
begin
    r1 <= r2;
    r2 <= r3;
    r3 <= in;
 end
endmodule

Regards

Adnan

[mcgett]

You have implemented 3 stage shift register that is 240 bits wide, so it takes 3 clock cycles for the original data to propogate through the chain. 

What were you expecting to happen?