Virtex® Family FPGAs

[udaranga]

I installed Xilinx 10.1 ise yesterday. But i can't synthesis any project. There are no syntax errors. But it give "synthesis fails".

I was using the same version before on the same laptop. I formatted it recently. So i had to reinstall it.

My OS : windows 7 64 bit

Given below is the console output.

___________________________________________________________________________________

Reading design: switch.prj

=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "switch.v" in library work
Module <switch> compiled
No errors in compilation
Analysis of file <"switch.prj"> succeeded.

=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <switch> in library <work>.

=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <switch>.
Module <switch> is correct for synthesis.

=========================================================================
* HDL Synthesis *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <switch>.
Related source file is "switch.v".
Unit <switch> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================

Loading device for application Rf_Device from file '5vlx30.nph' in environment C:\Xilinx\10.1\ISE.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
* Low Level Synthesis *
=========================================================================

Optimizing unit <switch> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block switch, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
* Partition Report *
=========================================================================

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
* Final Report *
=========================================================================

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 3.073ns

=========================================================================

Process "Synthesis" failed

[eteam00]

ISE 13.1 is the first release of ISE which officially supports Windows 7.  Suggest you make a backup copy of your project design files, and install version 13.4 or 14.1.

You do not need to uninstall the 10.1 release.  The 10.1 installation will not be compromised further by installing a more recent release of the toolset.

If it is paramount that you continue with using ISE 10.1, you might need to consider finding a Windows XP system to host the development tools.

-- Bob Elkind

[udaranga]

But the problem is. What I have is a vertex 2 board. But newer xilinx versions doesn't have that board. So i have to some how make 10.1 work.

I previously had xilinx 10.1 in windows 7.

[udaranga]

I also have 13.3 installed. It works properly. But i can put that bit file to vertex 2 board.

[eteam00]

I also have 13.3 installed. It works properly. But i can put that bit file to vertex 2 board.

Sorry, but no.  See this thread, which discusses which versions of ISE supports Virtex-2 devices.

Added to the New Users Forum README mini-FAQ:

"Classic" versions of ISE toolsets for old FPGA families

Table   Answer Record   ISE Classics download page    forum thread

-- Bob Elkind