Virtex® Family FPGAs

[gbredthauer]

Greetings,

I'm working on my first Virtex 6 DDR3 interface, and found in UG406 that I should compensate for internal per-pin delays using trace length matching on my PCB.  The user guide mentions that the "partgen" utility can be used to generate internal package trace lengths, but that sqrt(LC) calculations from the IBIS file are more accurate.  I did a comparison, and found that for my part (XC6VLX75T in FF784) the differences between the two techniques could be up to 20 ps or so, and UG406 says to match the delays to within 5 ps.

So, I'm using the IBIS calculations.  I wrote a little utility in Qt to calculate the per-pin delays in ps, and then put them into a spreadsheet.  For each pin I have:

A. Internal FPGA delay in ps

B. The internal delay converted to a board length (delay / propagation delay, propagation delay = c / sqrt(Er))

C. Existing trace length on the PCB (straight routing)

D. Total equivalent length for each trace (B + C)

E. For each byte group or control group, I choose the longest equivalent length

F. All other traces in a group are lengthened to equal (E - B)

If I'm doing this the correct way, I've posted the little IBIS delay extraction utility to assist others.  If not, I'd like to find out!

To use the extraction utility, just install the Qt SDK and then run qmake followed by make in a folder with extractdelays.pro and main.cpp.  I ran "extractdelays ff784_6vlx75t_ibs.pkg" and then opened the output delays.txt file in Excel.  I encourage you to double check at least a few of the pin delay results by hand!

Apparently this delay data is now available in a more user-friendly form for 7-series devices, but I did not see a simpler method for 6-series.

Cheers,

-Greg

[ywu]

Thanks for sharing this. Just wanted to mention that the flight time calculation from IBIS model has been available in ADEPT for Virtex6 and Spartan6 for a long time.

Calculate IO flight time using IBIS model

Spartan6 Pin Table View Enhancements in v0.44.2

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gbredthauer wrote:

Greetings,

I'm working on my first Virtex 6 DDR3 interface, and found in UG406 that I should compensate for internal per-pin delays using trace length matching on my PCB.  The user guide mentions that the "partgen" utility can be used to generate internal package trace lengths, but that sqrt(LC) calculations from the IBIS file are more accurate.  I did a comparison, and found that for my part (XC6VLX75T in FF784) the differences between the two techniques could be up to 20 ps or so, and UG406 says to match the delays to within 5 ps.

So, I'm using the IBIS calculations.  I wrote a little utility in Qt to calculate the per-pin delays in ps, and then put them into a spreadsheet.  For each pin I have:

A. Internal FPGA delay in ps

B. The internal delay converted to a board length (delay / propagation delay, propagation delay = c / sqrt(Er))

C. Existing trace length on the PCB (straight routing)

D. Total equivalent length for each trace (B + C)

E. For each byte group or control group, I choose the longest equivalent length

F. All other traces in a group are lengthened to equal (E - B)

If I'm doing this the correct way, I've posted the little IBIS delay extraction utility to assist others.  If not, I'd like to find out!

To use the extraction utility, just install the Qt SDK and then run qmake followed by make in a folder with extractdelays.pro and main.cpp.  I ran "extractdelays ff784_6vlx75t_ibs.pkg" and then opened the output delays.txt file in Excel.  I encourage you to double check at least a few of the pin delay results by hand!

Apparently this delay data is now available in a more user-friendly form for 7-series devices, but I did not see a simpler method for 6-series.

Cheers,

-Greg

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[gbredthauer]

Thanks for the heads up!  When I first started typing in inductances and capacitances by hand into Excel, I figured somebody must have automated this already.

[auricm]

Hi,

I'm designing the pcb for a virtex 6 device with 4 ddr3 ram components, it's the first time that I work with ddr3 components and I'm a little bit confused.
I'm following the JEDEC rules to mount directly on the pcb the ram, connecting the components in fly-by configuration topology, in the user guide ug406 I read that the data bus for each component must be short as possible, this sentence seems to me that's a little bit wrong, I read that between ram components the data bus must match, I'm wrong?

Thank you