Virtex® Family FPGAs

[singhabhishek]

Dear Sir, I am unable to download .rbt file through ICAP port(32 bit). I have generated two configurations by using FPGA editor, and then generated a difference bit file partial.rbt, which is loaded to block RAM instantiated in first configuration by JTAG interface. And then with a switch button on the board, the BRAM is made to load partial bit file in ICAP, but it is not working as expected. I think JTAG needs to be disabled but how?

Regards,

Abhishek Singh

[chenweit]

Abhishek, 

Assume you use iMPACT to load the initial config bitstream, iMPACT always relinquish control of config interface after it's done.

There are a few things that could affect ICAP. Please ensure you do not have PERSIST set in your bitstream. You should also check to see if your ICAP is setup for 8/16/32 bit interface. Also, you can take a look at the ICAP's output. When it successfully see a sync word, the status will be reflected.

http://www.xilinx.com/support/answers/8520.htm

Regards,
Wei

[singhabhishek]

Dear Sir,

                 In ICAP 32-bit mode, suppose a SYNC word X"AA995566" is to be written to ICAP, then it is written in straight order, but may you please tell clearly, how in ICAP 8-bit mode this is done taking the example of SYNC word only ?

Regards,

Abhishek Singh

[chenweit]

Abhishek, 

Please take a look at the UG and search for byte swap.

http://www.xilinx.com/support/documentation/user_guides/ug071.pdf

I've also noted a mistake in my prevkious post. V4 ICAP supports 8/32 interaface.

Regards,

Wei