Virtex® Family FPGAs

[tas-cortina]

I have a question regarding doing this safely.

I searched before posting this, and found some previous threads whose resolution I'd summarize as: "Should work OK if timing passes on the lowest speed grade, but Xilinx can't guarantee it, and be wary of any asynchronous circuits".  Which makes sense, but I seem to have a problem not covered in any of those threads.

I support a mix of -1 and -2 XC5VLX330 ASIC prototyping systems.  We started out on -1 HAPS-54 cards, and later on bought -2 cards when the supply of -1 dried up (hooray for improved yields!).

When I run trce against a .ncd created for a -1 part, forcing it to analyze as a -2, there are never any new setup violations (as expected), but there are often new hold violations.  This fits with what I can observe about how Virtex-5 P&R works: in the last few phases of routing, par appears to fix any hold time violations by adding route delay to data paths.  Since it's using -1 timing data to determine whether a hold time violation exists at all, it's plausible that par could miss hold violations which only exist in faster parts.

So, I gave up on generating a single bitfile and adjusted my build system to run map/par once per speed grade per FPGA.  This wasn't ideal from my point of view, as it chews up twice the CPU time in the backend and complicates the task of distributing FPGA images, but it worked.

What I think I'd like instead is a way to coax map and par into using -1 timing data for setup time analysis, and -2 data for hold.  Maybe that's crazy talk and it would never really work, but I'd like to know if (a) this is possible, (b) if it isn't now, whether Xilinx might consider adding it in future versions of the backend, and (c) if there's anything I'm missing.

Thanks!

[mcgett]

Any design that meets timing in a -1 speed grade will automatically meet timing a -2 part. And this is true for both setup and hold timing.

If the timing analyzer reported something different that would be a bug. Which ISE version are you using?

[tas-cortina]

I don't recall for sure which ISE version I was using when I originally encountered the issue -- it was about a year ago. It was probably either 12.1 or 12.4.

I just replicated it using 12.4. I have a -1 NCD built a few days ago which had complete timing closure (scores of 0 setup/hold). I reran trce with "-s 2" and it found 29 hold errors.

I went through the report and there is one thing in common between all the violations. This is an ASIC emulation design with 8:1 pin muxes for interconnect between FPGAs, and all the hold violations are on 8x/1x clock crossing paths inside the pin muxes.

I should also add that each 8x/1x clock pair is generated by 1 PLL and distributed with BUFG to ensure that they're fully synchronous. It looks like the maximum clock path skew for the violating paths is 425ps.

[tas-cortina]

Bump.  Should I file a WebCase to report this as a bug?

[mcgett]

Yes, you should open a webcase.  This should not be happening.