Virtex® Family FPGAs

[blapointe]

Hi,

I am trying to instantiate a 36x512 RAM module in my design.  Initially, in the Block Memory Generator I chose the memory type as "Simple Dual Port RAM".  This used 1 18K block RAM, which makes sense because 36x512 is the same number of bits as 18x1024.  Then, I realized that what I actually need is a true Dual Port RAM, so I changed the memory type to "True Dual Port RAM" but this seems to only use 36k block RAMs.  Even if I specify a 36x32 memory, it uses a 36k block RAM.  Has anyone else noticed this?  Is there any way to force it into an 18k block RAM?

Side question: When I look at the architecture of the Virtex5, I notice that each 36k block RAM is made up of two 18k block RAMs.  If I have two modules in my design that each use one 18k block RAM, is there any way to tell the Synthesizer/Implementer software to put them into the same 36k block RAM.  I would want to do this to reduce routing and to leave as many 36k block RAMs free for the rest of my design.  Does this make sense?

Thanks,

-Ben 

[gszakacs]

The problem with your 36-bit wide true dual port RAM is that at this width it

eats up the routing resources (total connections into the block) for the entire

36K block RAM.  It should still only use one 36K BRAM if it were 36 by 1K.

If you can somehow manage to live with 18-bit wide interface (e.g. 18 by 1024

instead of 36 by 512), then two should fit into the same 36K block.

HTH,

Gabor

[ywu]

RAMB18 (18k block ram) can only be set up to 18 bit wide in true dual port (TDP) mode (see the snapshot of Virtex5 UG below).

Yes, you can place two RAMB18s into the same RAMB36 site. Below are the constraints you can use in UCF:

Two RAMB18s can be placed in the same RAMB36 location by using the BEL UPPER/LOWER constraint:
INST ”my_ramb18_0” LOC = RAMB36_X0Y0 | BEL = UPPER;
INST ”my_ramb18_1” LOC = RAMB36_X0Y0 | BEL = LOWER;

Message Edited by jimwu on 02-16-2010 05:45 PM