V6 bitslip problems with ISERDES1
Hi everybody
I try to get the bitslip submodule to work, using ISERDES1. When I simulate my test design with Modelsim 10.0b I don't see any bitslip operation. Here is a waveform image I made:
My code for the ISERDES1 is the following:
library ieee;
use ieee.std_logic_1164.all;
Library unisim;
use unisim.vcomponents.all;
entity iserdes_test is
port(
clk_250_in : in std_logic;
clk_200_in : in std_logic;
clk_500_in : in std_logic;
rst_in : in std_logic;
data_in : in std_logic;
data_q : out std_logic_vector(3 downto 0);
bitslip_in : in std_logic;
ready_q : out std_logic
);
end entity iserdes_test;
architecture rtl of iserdes_test is
signal data : std_logic_vector (3 downto 0) := "0000";
signal sample_clk_500 : std_logic := '0';
signal n_sample_clk_500 : std_logic := '1';
signal ctrl_rdy : std_logic := '0';
begin
ISERDES_inst : ISERDESE1
generic map (
DATA_RATE => "DDR", -- "SDR" or "DDR"
DATA_WIDTH => 4, -- Parallel data width (2-8, 10)
DYN_CLKDIV_INV_EN => FALSE, -- Enable DYNCLKDIVINVSEL inversion (TRUE/FALSE)
DYN_CLK_INV_EN => FALSE, -- Enable DYNCLKINVSEL inversion (TRUE/FALSE)
INIT_Q1 => '0', -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING", -- "MEMORY", "MEMORY_DDR3", "MEMORY_QDR", "NETWORKING", or "OVERSAMPLE"
IOBDELAY => "NONE", -- "NONE", "IBUF", "IFD", "BOTH"
NUM_CE => 1, -- Number of clock enables (1 or 2)
OFB_USED => FALSE, -- Select OFB path (TRUE/FALSE)
SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE"
SRVAL_Q1 => '0', -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map (
O => open, -- 1-bit output: Combinatorial output
-- Q1 - Q6: 1-bit (each) output: Registered data outputs
Q1 => data(0),
Q2 => data(1),
Q3 => data(2),
Q4 => data(3),
Q5 => open,
Q6 => open,
-- SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => bitslip_in, -- 1-bit input: Bitslip enable input
-- CE1, CE2: 1-bit (each) input: Data register clock enable inputs
CE1 => '1',
CE2 => '0',
-- Clocks: 1-bit (each) input: ISERDESE1 clock input ports
CLK => sample_clk_500, -- 1-bit input: High-speed clock input
CLKB => n_sample_clk_500, -- 1-bit input: High-speed secondary clock input
CLKDIV => clk_250_in, -- 1-bit input: Divided clock input
OCLK => '0', -- 1-bit input: High speed output clock input used when INTERFACE_TYPE="MEMORY"
-- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion input
DYNCLKSEL => '0', -- 1-bit input: Dynamic CLK/CLKB inversion input
-- Input Data: 1-bit (each) input: ISERDESE1 data input ports
D => data_in, -- 1-bit input: Data input
DDLY => '0', -- 1-bit input: Serial input data from IODELAYE1
OFB => '0', -- 1-bit input: Data feedback input from OSERDESE1
RST => rst_in, -- 1-bit input: Active high asynchronous reset input
-- SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
SHIFTIN1 => '0',
SHIFTIN2 => '0'
);
sample_clk_500 <= clk_500_in;
n_sample_clk_500 <= not clk_500_in;
data_q <= data;
ready_q <= ctrl_rdy;
end architecture rtl;
And the testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end entity tb;
architecture behavior of tb is
component oserdes_test is
port(
clk_250_in : in std_logic;
clk_500_in : in std_logic;
data_in : in std_logic_vector(3 downto 0);
data_q : out std_logic;
rst_in : in std_logic
);
end component oserdes_test;
component iserdes_test is
port(
clk_250_in : in std_logic;
clk_200_in : in std_logic;
clk_500_in : in std_logic;
rst_in : in std_logic;
data_in : in std_logic;
data_q : out std_logic_vector(3 downto 0);
bitslip_in : in std_logic;
ready_q : out std_logic
);
end component iserdes_test;
constant CLK_200_PERIOD : time := 5 ns;
constant CLK_250_PERIOD : time := 4 ns;
constant CLK_500_PERIOD : time := 2 ns;
signal clk_200, clk_250, clk_500 : std_logic := '0';
signal data, data_del : std_logic := '0';
signal trans_data : std_logic_vector(3 downto 0) := "0001";
signal recv_data : std_logic_vector(3 downto 0) := "0000";
signal ready, bitslip : std_logic := '0';
begin
clk_200_proc: process
begin
clk_200 <= '0';
wait for CLK_200_PERIOD / 2.0;
clk_200 <= '1';
wait for CLK_200_PERIOD / 2.0;
end process;
clk_250_proc: process
begin
clk_250 <= '0';
wait for CLK_250_PERIOD / 2.0;
clk_250 <= '1';
wait for CLK_250_PERIOD / 2.0;
end process;
clk_500_proc: process
begin
clk_500 <= '0';
wait for CLK_500_PERIOD / 2.0;
clk_500 <= '1';
wait for CLK_500_PERIOD / 2.0;
end process;
main_proc: process
begin
wait for 40 ns;
bitslip <= '1';
wait for 4 ns;
bitslip <= '0';
end process;
data_del <= transport data after 0.5 ns;
transmit: oserdes_test
port map(
clk_250_in => clk_250,
clk_500_in => clk_500,
data_in => trans_data,
data_q => data,
rst_in => '0'
);
receive: iserdes_test
port map(
clk_200_in => clk_200,
clk_250_in => clk_250,
clk_500_in => clk_500,
rst_in => '0',
data_in => data_del,
data_q => recv_data,
bitslip_in => bitslip,
ready_q => ready
);
end architecture behavior;
Some words about the clocks:
clk_500 is the highspeed clock, for sending the data from OSERDES, clk_250 is the divided clock for ISERDES1 and clk_200 is a reference clock for using idelay_ctrl (not implemented yet).
I read the UG361 but I can't see the problem. When I understand the UG correctly, then I only have to set the INTERFACE_TYPE to NETWORKING. In Figure 3-14 is an example timing diagram, and I can't find the difference between the example and my design, so I hope someone can help me.
Thanks a lot and have a nice weekend.
Best reagrds,
Tobias
Thanks a lot.
Now the bitslip module do something. But I'm a bit confused of the results. I made a simple example, you can see in the picture above:
In UG361, the behavior of the bitslip operation as explained with:
1.) 1 bit rotation right
2.) 3 bit rotation left
3.) 1 bit rotation right
4.) 3 bit rotation left
5.) and so on
So with data 0100, I would expect the data 0100, 0010, 0001, 1000, 0100 and so on. But I see 0100, 0010, 1000, 0010, 0100, and so on. I never get the case 1000 but 0010 twice.
What could be the explanation for this behavior?
Cheers,
Tobias
After reading your answer I had the same idea. But it shows a better behavior than letting the bitslip constantly high:
(I hope the pictures are good enough.)
Here I got the expected results, but 0100 before the 0001 shouldn't be, but the rest seems like I expect. A bit confusing is example in UG361 figure 3-14. There they let bitslip on constantly high, for doing two bitslip operations.
