Virtex® Family FPGAs

[zzww200]

use the vertex-4 xc4vsx55 device. In my design I want to use  an IO standard of LVCMOS25 IO pins receive the LVCOMS3.3,how shoud i do ? i want a series resistance of 300Ω  to work, is it suitable?

[gszakacs]

I believe there are a number of threads on this topic.  Whether or not this will work

depends to some extent on the speed of the 3.3V signals.  The 300 ohm series

resistance, even if the resistor is placed close to the V4 chip will slow down the

edge rates.  Also even though it is OK to drive up to 10 mA of current into the Vcco

clamp diodes, doing so will also add to the edge delay when the input signal

switches low.  If the signals are essentially static, this doesn't matter.  Another

issue is the number of 3.3V I/O's you need to connect, because the currents

into the clamp diodes will add up and this may disturb the Vcco power supply,

especially if it is not designed to sink current (like an LDO regulator).

Two other approaches come to mind:

1) Use two resistors as a voltage divider so you don't turn on the clamp diodes.  For

example if your input can source 8 mA you could use 100 Ohms in series with the

driver and 300 ohms from the V4 input side of this to ground.  For slower signals sampled

less frequently by the V4 chip you could use larger resistors.

2) Insert a level shifter IC between the input signal and the V4.  This may be necessary

for high-speed signals.

-- Gabor

[zzww200]

thanks .

i fand Virtex-6 FPGA Application Notes XAPP899 describes methodologies for interfacing Virtex®-6 devices to 3.3V systems. Virtex-4 ??

[eteam00]

If the signal is strictly an input, have you considered using a simple resistor divider to scale a 3.3V logic signal to 2.5V?  Is there enough headroom on the minimum VOH for the signal source, after it is scaled?

-- Bob Elkind

[gszakacs]

---

zzww200 wrote:

thanks .

i fand Virtex-6 FPGA Application Notes XAPP899 describes methodologies for interfacing Virtex®-6 devices to 3.3V systems. Virtex-4 ??

---

XAPP 889 was written for Virtex 6 because V6 does not have the option of using Vcco of 3.3V and its

inputs are not 3.3V tolerant.  However the methods in XAPP 889 apply to other FPGA's with 2.5V Vcco

as well, including Virtex 4.

-- Gabor