Virtex® Family FPGAs

[suddy72]

Hi people,

I previously post a question about core generator and with the help i recieved i managed to solve the problem.

I have created a memory module with writes data to its specific locations.

Does anyone know how you view the data that has been written to thse locations. What i am trying to do is take the data from this memory location and view it on my PC so i can then analyze it in MatLab.

So just to clarify i , my question is how do you take the data from the core gen memory and get it to appear on the PC in an array or whatever other format..

Thanks again,

Stuart

[martinthompson]

Stuart,

If you have modelsim, you can view the memory in the list window at some point during your simulation, and I think you can copy/paste the values, or dump them to a textfile.

Personally, I avoid coregen for memories, just infer them.  Then if I need to see what's going on, I can put print statements in my HDL code, with a unique prefix and then grep them our of the logfiles for further processing.

Cheers,
Martin

[unicorn70]

To analyze the data with Matlab, my first thought would be System Generator.
Sysgen can comunicat with the FPGA Board and Matlab.
I don't know deep of this tool. You can open a WebCase to the Xilinx experts.

For general usage, a UART is also easy to implement in FPGA.
Use UART to send out data to PC.
There are a lot of SCom tools to receive data from UART.
Then you can copy/paste data to Matlab.

[martinthompson]

Stuart,

You sent me an emil about htis yesterday, but I fumbled my reply (Groupwise has the short cut for "shred irretrievably" on the key next to "Reply" - I need to get a hex editor on the executable I think!) and I've now lost your mail.

Please resend it and I'll reply (hopefully!)

Cheers,
Martin