Virtex® Family FPGAs

[awillen]

In the Virtex-5 DSP user guide (UG193), page 38, the operation of the embedded 25x18 signed multiplier is described as producing two 43-bit partial products, which are concatenated to a 86-bit result.

A 25x18 signed multiplication result fits within a 43-bit two's complement (i.e., signed) number, so what's with the two "partial" products and the "86-bit result"?

By the way, it says the same in the Virtex-6 DSP48E1 user guide.

Adrian

[jotta]

It's the same for V4,V5,V6 ((except 18x18 multiplier for V4), they all outputs two partial

products. These are fed into the X- and Y-MUX and add  together in the Adder-stage

(this is the reason why you have to choose the same setting for both X- and Y-MUX

in the case of multiplier use).

With other words: The Multiplier doesn't produce the complete product, this is the

result of the adder.

[awillen]

 Let me clarify: for a 25x18 multiplication, the complete result fits into 43 bits, so there's no need for the upper 43 bits – they would always be the sign-extension of the lower 43 bits. That's why I don't understand why a "86-bit result" is mentioned.

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The Multiplier doesn't produce the complete product, this is the result of the adder.

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What do you mean by that?

Adrian

[jotta · Accepted solution]

That a 25x18 product needs 43 bits should be clear. I guess you interprete partial products

with some kond of lower and upper bit vector. But it's not an lower/upper partitition, it's some

kind of (maybe) additive partitition (the exact meaning of xilinx's "partial product" is nowhere

mentioned).

Assume e.g. that you want to multiply A*B = C  (A,B are 16 bit vectors, so C is 32 bit long).

Set A = A1A0, B=B1B0 and C0 = A0*B, C1 = A1*B, then C = C1C0 = C1 << 8 + C0  (<<: shift operator!).

Set P0 = C0,  P1 = C1 << 8 (both sign-extended!), then P0,P1 are partial products of length 32,

together 64 bits total (this are your 86-Bits). This 2*32 bits are then fed into the X- and Y-MUX

and add together to form the final product.

Instead of additive partition there are also other partititions posible, as long as the adder-stage

(includes also logic operations) can handle that. But I would guess it's additive.

Joe

[awillen]

Thank you, Joe, now I understand! I never considered that the multiplier might use the adder to complete the multiplication. And yes, I interpreted "partial products" as the two parts of the result bitvector.

There are just a couple of inconsistencies (in the documentation, not in your explanation):

1. Only one partial product needs 43 bits (P1), the other one (P0) needs fewer bits. So why are both described as "43-bit"? After all, they have to be sign-extended to 48-bit anyway.
2. X and Y are 48-bit multiplexors, so why not say that they are 48-bit partial products?
3. Why is this confusing, rather useless, piece of implemenation information included in the user guide anyway? :smileywink:

Adrian

[jotta]

Hi Adrian,

1. In my example, P0 needs less bits than P1, but this is only due to my definition of "partial". You

can also split A into odd and even bits with partial results Q0,Q1 of more ore less same length...

but this will stay a Xilinx' secret.

2. Only my opinion: X- and Y-MUX are not pure MUX, they are a little bit more (e.g. also 17-bit-shifter

and sign-extender). The 48-Bit-Extension is neccessary for the Adder (see Formula Z+(X+Y+CIN)..)

I myself interprete the DSP as two Engines, a multiplier and an adder. The X-/Y-/Z-MUXes build the

interface between them and so they are responsible for the 43- to 48-Bit extension.

3. I've an older V4-DSP pdf in mind, it defines the whole scenario with the 86-bit-problem more clearly.

But with each new VirtexXYZ-generation, this informations are aranged in a suprisingly new way (lol).

In the V4-pdf, there is a C+(A+B+CIN)-Formula with A,B as partial products and an consistent definition.

Good Luck with your math,

Joe