Virtex® Family FPGAs

[dawatson]

Hi all

I've been searching the forums and web for around 2 weeks now for a simple guide on how to include and configure the xps_tft core for the XUPV5 and all I have so far is random pieces of information. The problem is made worse by the fact that XPS13.1 doesn't fully support the XUPV5. Therefore, you have to create your project for the ML505 and change the chip and constraints manually. So far, here is my understanding for including the xps_tft ip:

1. Add the ip to the design, base address in DDR2 (normally 0x90000000), connect to PLB, and make HSYNC, SYNC, etc. external
2. Add IIC ip and make SCL and SDA external
3. Add a custom reset line to the xps_tft ip so it enables it when system reset is '0'

The kicker is modifying the .ucf file. I've got bits bits and bobs from the ML505 example but there are some warnings when updating the bitstream. I'd rather clarify what I'm doing before I go ruining the board!

If anyone can describe the changes required to .ucf file for the XUPV5 it'd be much appreciated. And if they could say whether or not this is correct up to this point that'd also be good!  I'll include the .ucf file (as a .txt file) as it stands just now.

Thanks for your help

David

[austin]

David

The BSB designs for that board are on the website, and they have their ucf files, and profiles that you can bring into PlanAhead, or EDK.

http://www.xilinx.com/univ/xupv5-lx110t-refdes.htm

Do not start with any ML505 files:  start with the above files!  Also, as you know, the xc5vlx110t requires a license, but if you are a student, these are provided to you through the XUP.

[dawatson]

Thanks Austin!

I'll give those designs a bash and see where I get to. I've got a licence for the full 13.1 ISE, but whenever I used the xc5vlx110t I get: 
INFO:Security:56 - Part 'xc5vlx110t' is not a WebPack part.

Does that mean I'm using the wrong  IDE?

Thanks again

David

[austin]

David,

As I mentioned, you need a license.  Webpack does not support the 110t (in any version of ISE).

[dawatson]

Hi Austin

I do have a licence but I've no idea what the difference between the full ISE and webpack ISE is. Surely if I copied the licence during the installation I should have the full ISE?

[austin]

Even webpack requires a license.

But, it was free.

To get the license for the 110t, you need to request it from your professor (TA), or buy one from Xilinx.

[dawatson]

Hi Austin

Is there a reason that a pcore is used for displaying rather than the xps_tft display ip? I'd also recommend updating the designs to accomodate the newer ISE as the designs have to be rebuilt and then the majoirty of the ip has to be added manually as the XPS cannot do so for some reason.

Thanks

David 

[dawatson]

Just a quick update. I managed to get the xps_tft core working with the XUPV5.

Thanks for your help

[eteam00]

Just a quick update. I managed to get the xps_tft core working with the XUPV5.

For those who search the forums looking for answers to their problems, would you mind describing how you managed to get the xps_tft core working with the XUPV5?

Also, please mark this thread as 'solved'.  Thank you!

-- Bob Elkind

[dawatson]

Hi Bob

I don't have it fully working yet. I can get it to display on the screen but its not the correct display. I'm debugging just now but I'll give a guide to the steps thus far. If anyone can spot what's going wrong that'd be extra good!

1. Add xps_tft ip to your design, both buses go to the PLB, starting memory address = 0x90000000. Under ports make HSYNC, VSYNC, DVI_DATA, DVI_CLK_N, DVI_CLK_P, DE, IIC_SCL, and IIC_SDA external
2. Add IIC ip to design, attach to PLB, make SCL and SDA external
3. Add vector utlity logic, make it a 'not' gate with width 1. Create a new external port, call it 'vga_reset_pin' and give it the net 'sys_periph_reset_n'
4. In the ports tab, for the  vector logic, connect Op1->sys_periph_reset, and Res->sys_periph_reset_n
5. Generate addresses

6. Can use the .ucf file I've attached if you've used the same naming convention. Note I used a small design to speed up the bitstream. Therefore, my design only has a Microblaze, with 1 UART, DDR2, and the lmb controllers.

7. Use the clock wizard to set the xps_tft sys_tft_clk to 25MHz and the slowest sync clock to 25MHz 
8. Update bitstream and export to SDK

Using a colour bar example you'll get some output but unforunately it won't be right. If anyone knows what I've done wrong please point it out!

Thanks 

David