Virtex® Family FPGAs

[heiyux]

Hi there,

I‘ve got two questions of Virtex-6 Clock resoure.

1, In ug362, we learn that “the span of a regional clock signal (BUFR) is limited to three clock regions(page26, line3)”, and there is a HROW in the center of every clock region. Then, let’s see Figure 1-2 in page 11(see the picture followed), the HROW in the center of the two banks is indicated as a BLACK LINE which goes cross the CMT. Is this suggesting that the HROW in the clock region is connected to the opposite region crossed the CMT? Or this is just a  misdrawing?

2, When I use ISERDES without MMCM, the source-synchronous input clock will be buffered by a BUFIO to clock all the ISERDESs. According to ug362, BUFIOs can only be driven by clock-capable I/Os located in the same bank and two BUFIOs in the bank can drive the regions above and below. So I can only use MRCC pins since I use many data IOs which cross banks. I can't use SRCC, regular IO, or GC pins for input clock, the compilation will fail.  So here‘s the question, if I remove the BUFIO between the input clock and ISERDES, then I found all SRCC, regular IO, or GC pins can be use for input clock, the compilation will all end successfully. What's the affect if I don't use BUFIO? Is the clock region concept only accept in BUFIO or some particular elements? Why ISE doesn't report anything when I use none clock-capable IO as a clock input to dirve internal circuit or SRCC to dirve another region’s circuit?

Thanks for attention!

Any relatived advice will be appreciated！

Regards,

Day

[austin]

h,

Don't get stuck with that figure:  move onto figure 1-22 on page 28.

[heiyux]

Thanks, Austin! 

I've got it about the figure.

And Do you have any idea about my second question?

Regards,

Day

[austin · Accepted solution]

Day,

I don't know.

I would use FPGA_editor to look at the design.  You will be able to see what IO can, and can't be done.  I often use FPGA_editor to get a better idea of how the resouces may be utilized.  The user's guides represent the best practices, and often using something that is not in the guide will work just as well:  we may not have done it that way, but it will still work.

Warnings are reported for usage that is not optimal, or perhaps just bad practice (like using a non-clock input pin, and regular interconnect to get to MMCM).

Errors represent something that the tools cannot do:  the resource is unable to be used that way.

[kren]

1. No. The HROW is in each clock region. They're driving by global clock through BUFG/BUFH.

2. You can use SRCC if all the data pins are in the same bank. You can also use BUFG to register the input data. The error reported in ISE if dedicated clock routing is not used.

[heiyux]

Thanks Austin!

I'll check it out in FPGA editor. First I need to learn how to use it, cause I haven't never used it yet. :)

Thanks kath!

I'll take a further checking on it.