05-30-2012 04:27 AM
Dear Xilinx people,
I have some simple questions to ask. I am working on a PCB design using Virtex 6 SX475T.
I am considering to add an expansion port which has 2 pairs of CML and 6 pairs of LVDS signals.
From the user guide, i think the one GTX bank can handles the 2 pairs of CML (input / output).
However, can GTX generate and receive LVDS signals? or have to use I/O bank to handle the LVDS signals?
Thank you for answering.
05-30-2012 09:14 AM
The GTX are for high speed serial protocols/interfaces. What protocal are you planning on using on this expansion port?
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05-30-2012 05:07 PM
The target device is to connect to the Ettus USRP Networked Series. It has a MIMO expansion port allowing multiple USRP N200 series devices to be synchronized and used in a MIMO configuration. We consider to put such connector on the PCB as an option first. That's why I am reading for the appropriate connections.
In its schematic, it uses Spartan 3A-DSP. For the CML pairs (1 x input and 1 x output), it inserts TI TLK2701 1.6 to 2.7 GBPS Transceiver in between FPGA and connector, that will convert between LVTTL <-> CML. I have not study their FPGA source codes to find out how they configure the TLK2701. If the GTX can be configured to generate compatible CML signals, it can replace the external TLK2701.
For the LVDS pairs, it uses the FPGA I/Os as Spartan does not have GTX. That is what I am not sure whether GTX can be used to handle LVDS signals.
05-30-2012 05:43 PM
I have another question to ask, my Virtex SX475T is connected to a TI ARM processor.
This ARM processor has one PCI Express 2.0 port with integrated PHY
– Single Port With 1 or 2 Lanes at 5.0 GT/s
– Configurable as Root Complex or Endpoint
By using 2 transceiver pairs in one GTX quad, it can be configured to support PCIe 2.0 link, is that right?
There is a clocking IC that gives 100MHz differential clock to that quad MGTREFCLK0P/N and ARM.
Anyway, document or note that faciliate the FPGA development in supporting PCIe 2.0?
Thank you for your answer.