Simple question: If I give a V6 (-2 speed grade) IODELAYCTRL a 250 MHz refclk, do I get a properly calibrated tap delay which lies somewhere between the listed datasheet values of 78ps @ 200 MHz and 52ps @ 300 MHz? If so, is the tap delay linear WRT refclk frequency? (i.e. 65ps @ 250)
The reason I'm asking: I have a situation where I have to synthesize the IODELAYCTRL reference from a clock input which is either 125 MHz or 156.25 MHz, depending on how fast we want to run the datapath in a multi-FPGA system, and the FPGA has no way of sensing which it is. Right now, the workaround is to build 2 versions of one of the FPGAs, identical except for the M/D ratio on a single MMCM. If I built a single version using a 1.6x ratio, that would give me either 200 or 250 MHz depending on the input frequency. If 250 is an acceptable IDELAYCTRL reference, with a predictable average tap value, I can figure out if that provides enough IODELAY range for our application, and then maybe we don't have to build two versions any more.
